Integra DTR-7.8 Service Manual page 136

QQ
3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -34
Q3551 : ES29LV400ET-70TG (4 Mbit Flash Memory)
BLOCK DIAGRAM
Vcc
Vss
WE#
RESET#
A<0:17>
TE
L 13942296513
CE#
OE#
BYTE#
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.
http://www.xiaoyu163.com
RY/BY#
Timer/
Vcc Detector
Counter
Write
Command
State
Register
Machine
Chip Enable
Output Enable
Logic
x ao
y
i
http://www.xiaoyu163.com
8
Analog Bias
Generator
Sector Switches
Q Q
3 6 7 1 3
u163
.
2 9 9 4 2 8
DQ0-DQ15(A-1)
Input/Output
Buffers
Data Latch/
Sense Amps
Y-Decoder
Y-Decoder
1 5 0 5 8 2 9 9 4
X-Decoder
Cell Array
m
co
DTR-7.8
9 9
2 8 9 9