Integra DTR-7.8 Service Manual page 141

QQ
3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -39
Q3461, Q3471, Q3561: IC42S16100 (16-Mbit Synchronous Dynamic RAM)
BLOCK DIAGRAM
CLK
CKE
COMMAND
CS
DECODER
RAS
&
CAS
CLOCK
WE
GENERATOR
A11 1
A10
A9
REFRESH
CONTROLLER
A8
A7
A6
REFRESH
A5
COUNTER
A4
A3
A2
A1
A0
ADDRESS
11
TE
L 13942296513
PIN CONFIGURATION
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MODE
REGISTER
11
SELF
REFRESH
CONTROLLER
ROW
LATCH
VCC 1
I/O0 2
I/O1 3
GNDQ 4
I/O2 5
I/O3 6
VCCQ 7
I/O4 8
I/O5 9
GNDQ 10
I/O6 11
I/O7 12
VCCQ 13
LDQM 14
WE 15
CAS 16
RAS 17
CS 18
A11 19
A10 20
A0 21
A1 22
A2 23
A3 24
x ao
VCC 25
y
i
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8
ROW
ADDRESS
2048
BUFFER
11
11
8
8
2048
ROW
ADDRESS
BUFFER
11
11
Q Q
3 6 7 1 3
50 GND
49 I/O15
48 I/O14
47 GNDQ
46 I/O13
45 I/O12
44 VCCQ
43 I/O11
42
I/O10
41 GNDQ
40 I/O9
39 I/O8
38 VCCQ
37 NC
36 UDQM
35 CLK
34 CKE
33 NC
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
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26 GND
.
2 9 9 4 2 8
MEMORY CELL
ARRAY
BANK 0
DATA IN
SENSE AMP I/O GATE
BUFFER
16
256
COLUMN DECODER
256
DATA OUT
SENSE AMP I/O GATE
BUFFER
16
MEMORY CELL
ARRAY
BANK 1
1 5 0 5 8 2 9 9 4
m
co
DTR-7.8
9 9
DQM
16
I/O 0-15
16
Vcc/VccQ
GND/GNDQ
2 8 9 9