Integra DTR-7.8 Service Manual page 138

QQ
3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -36
Q3651 : ES29LV800ET-70TG (8 Mbit Flash Memory)
BLOCK DIAGRAM
Vcc
Vss
#
WE
RESET#
A<0:18>
TE
L 13942296513
CE#
OE#
BYTE#
www
.
http://www.xiaoyu163.com
RY/BY#
Timer/
Vcc Detector
Counter
Command Write
State
Register
Machine
Chip Enable
Output Enable
Logic
x ao u163
y
i
http://www.xiaoyu163.com
2 9
8
Analog Bias
Generator
Sector Switches
Y-Decoder
Q Q
3 6 7 1 3 1 5
X-Decoder
co
.
9 4 2 8
DQ0-DQ15(A-1)
Input/Output
Buffers
Data Latch/
Sense Amps
Y-Decoder
0 5 8 2 9 9 4 2 8
Cell Array
m
DTR-7.8
9 9
9 9