Integra DTR-7.8 Service Manual page 175

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -73
Q103 : F2628E-01 (XM Digital Transceiver)
BLOCK DIAGRAM
COMM_TX_P
COMM_TX_M
COMM_RX_P
COMM_RX_M
LINKACTIVE (M=o, S=o)
COMM_TX_EN (M=o, S=o)
OSC_OUT
TE
L 13942296513
PIN CONFIGURATION
RFU (I2C_SCL)
RFU (I2C_SDA)
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3.3V
GND
OSC_IN
OSC
LSDP 1
VSS 2
SC_TX_OUT 3
VDD 4
SC_RX_IN 5
6
7
VDD 8
ANT_REV 9
10
VSS
11
RESET#
SLAVE_SEL 12
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8
Inter-IC
Sound
(I2S)
High Speed
Data Port
(HSDP)
Low Speed
Data Port
(LSDP)
SAII
Sys Ctrlr
(CBM)
Bus I/F
Misc Status
Q Q
& Control
RAM
3 6 7 1 3
36
35
34
33
32
31
XM/DT IC
30
29
28
27
26
25
u163
.
2 9 9 4 2 8
I2S_OCLK (M=o, S=n/u)
I2S_LRCLK (M=o; S=i)
I2S_SCLK (M=o; S=i)
I2S_DATA (M=o; S=i)
I2S_RATE (M=o, S=n/u)
MUTE (M=o, S=n/u)
HSDP_EN# (M=o; S=i)
HSDP_CLK (M=o; S=i)
HSDP_DATA (M=o; S=i)
LSDP (M=o; S=i)
SAII_REQ (M=i; S=o)
SAII_CLK (M=o; S=i)
SAII_DATA (M=o; S=i)
SC_RX_IN (M=i, S=i)
SC_TX_OUT (M=o, S=o)
SC_RATE (M=i, S=o)
RESET# (M=i, S=i)
ANT_REV (M=o,S=n/u)
DT4_MODE (M=i, S=i)
SLAVE_SEL (M=i, S=i)
1 5 0 5 8 2 9 9 4
TEST (M=i, S=i)
(RFU –I2C_SCL)
(RFU –I2C_SDA)
HSDP_EN#
DT4_MODE
HSDP_CLK
VDD
HSDP_DATA
VSS
TEST
SC_RATE
OSC_IN
VDD
OSC_OUT
VSS
m
co
DTR-7.8
9 9
2 8 9 9