Integra DTR-7.8 Service Manual page 157

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -55
Q8801: ADV7172 (Digital PAL/NTSC Video Encoder with six DACs)
BLOCK DIAGRAM
CLOCK PAL NTSC
FIELD/
TTX
TELETEXT
INSERTION BLOCK
TTXREQ
V
AA
P0
4:2:2 TO
4:4:4
COLOR
INTER-
DATA
POLATOR
P7
TE
L 13942296513
PIN CONFIGURATION
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CLAMP SCLOCK SDATA
VIDEO TIMING
GENERATOR
BRIGHTNESS AND
CONTRAST CONTROL
+
ADD SYNC
Y
8 8
+
INTERPOLATOR
YCrCb
8
TO U
SATURATION CONTROL
YUV
+
8
MATRIX
ADD BURST
8 V +
8
INTERPOLATOR
48 47 46 45 44
1
V
AA
PIN 1
P0 2
IDENTIFIER
P1 3
4
P2
5
P3
P4 6
P5 7
8
P6
P7 9
10
CSO_HSO
V 11
AA
GND 12
13 14 15 16 17 18 19 20 21 22 23 24
x ao
y
i
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8
ALSB
2
I C MPU PORT
LUMA
PROGRAMMABLE
10
FILTER
+
SHARPNESS
FILTER
10
PROGRAMMABLE
CHROMA
10
FILTER
REAL-TIME
CONTROL CIRCUIT
SCRESET/RTC GND
Q Q
3 6 7 1 3
43 42 41 40 39 38 37
36
35
34
33
32
ADV7172
31
30
TOP VIEW
29
28
27
26
25
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2 9 9 4 2 8
M
10 10
U
10-BIT
YUV TO
L
DAC
RBG
T
MATRIX
10
I 10
+ 10-BIT
P
YUV DAC
L
LEVEL
E
10 10
CONTROL
10-BIT
X
BLOCK
DAC
E
R
DAC
CONTROL
M
BLOCK
U
L
10
10-BIT
T
DAC
I
10
P
10
MODULATOR
L 10-BIT
10
+
E DAC
HUE
X
CONTROL 10 10
E
10-BIT
R
DAC
10 10
DAC
SIN/COS
CONTROL
DDS BLOCK
BLOCK
1 5 0 5 8 2 9 9 4
COMP1
DAC A
V
AA
DAC B
V
AA
GND
V
AA
DAC C
DAC D
V
AA
GND
DAC E
m
co
DTR-7.8
9 9
DAC A
DAC B
DAC C
V
REF
R
SET2
COMP2
DAC E
DAC F
DAC D
R
SET1
COMP1
2 8 9 9