Integra DTR-7.8 Service Manual page 124

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -22
Q3501: D788E001BRFP266/D708E001BRFP266 (Audio DSP)
BLOCK DIAGRAM
Device Block Diagram
C67x+ CPU
I/O
TE
L 13942296513
I/O Interrupts
System Diagram
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.
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D1
Data 64
R/W
D2
Memory
Data 64
Controller
R/W
Program
INT Fetch
Program
Cache 256
PMP DMP
32K Bytes
32
High-Performance
Crossbar Switch
32 32
MAX0 CONTROL MAX1
Out
dMAX
DSP
256K
Bytes
C67x+
RAM
DSP Core
768K
Bytes
Program
ROM
Cache
Crossbar Switch
EMIF dMAX
ASYNC
FLASH
x ao
y
Host
Microprocessor
i
100-MHz/
133-MHz
SDRAM
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8
Program/Data
256 RAM
256K Bytes
Program/Data
256 ROM Page1
256K Bytes
Program/Data
256 ROM Page2
256K Bytes
Program/Data
256 ROM Page3
256K Bytes
CSP 32 32
32
32 32
Q Q
3 6 7 1 3
Events
In
EMIF
Peripheral Interrupt and DMA Events
Audio Zone 1
McASP0
SPI or I2C
SPI1
Control (optional)
I2C0
Audio Zone 2
McASP1
Audio Zone 3
McASP2
SPIO
I2C1
RTI
PLL OSC
DSP Control
u163
SPI or I2C
.
2 9 9 4 2 8
JTAG EMU
McASP0
32
16 Serializers
32
32
McASP1
6 Serializers
32
32 McASP2
2 Serializers
32 DIT Only
32 SPI1
32 SPI0
32 I2C0
32
32 I2C1
32 RTI
1 5 0 5 8 2 9 9 4
32 PLL
CODEC, DIR,
ADC, DAC, DSD,
Network
CODEC, DIR,
ADC, DAC, DSD,
Network
Digital Out
5 Independent Audio
Zones (3 TX + 2 RX)
16 Serial Data Pins
m
co
DTR-7.8
9 9
2 8 9 9