Integra DTR-7.8 Service Manual page 151
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Also See for DTR-7.8:
- Instruction manual (128 pages) ,
- Instruction manual (128 pages) ,
- Service manual (339 pages)
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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -49
Q8001: FLI8125-LF-BC (Video Processor)
TERMINAL DESCRIPTION(5/8)
System Interface
Pin Name
GPIO13/PWM2
GPIO14/PWM3/
SCART16
TDO
HSYNC1
VSYNC1
XOSD_CLK
XOSD_HS
XOSD_VS
XOSD_FLD
PD20/B4/GPIO0
PD21/B5/GPIO1
PD22/B6/GPIO2
PD23/B7/GPIO3
LVDS Display Interface
Pin Name
TE
L 13942296513
PBIAS
PPWR
AVDD_LV_33
VCO_LV
AVSS_LV
AVDD_OUT_LV_33
CH3P_LV_E
CH3N_LV_E
CLKP_LV_E
CLKN_LV_E
CH2P_LV_E
CH2N_LV_E
CH1P_LV_E
CH1N_LV_E
CH0P_LV_E
CH0N_LV_E
AVSS_OUT_LV
AVDD_OUT_LV_33
CH3P_LV_O
CH3N_LV_O
CLKP_LV_O
CLKN_LV_O
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CH2P_LV_O
CH2N_LV_O
CH1P_LV_O
.
CH1N_LV_O
CH0P_LV_O
CH0N_LV_O
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No
I/O
Description
51
IO
This Pin can be programmed to give out Pulse Width Modulated Output Pulses for
external use. Else, this pin is available as General Purpose Input/output Port.
52
IO
This Pin can be programmed to give out Pulse Width Modulated Output Pulses for
external use. Or it can be programmed to sense the Fast Blank Input signal from a
SCART I/P source. Else, this pin is available as General Purpose Input/output Port.
55
O
This Pin provides the Output Data in case of Boundary Scan Mode.
156
I
Horizontal Sync signal Input-1. Used when Analog RGB component signal carries
separate HSYNC signal. Has programmable Schmitt trigger.
157
I
Vertical Sync signal Input-1. Used when Analog RGB component signal carries separate
VSYNC signal. Has programmable Schmitt trigger.
101
O
Clock Output meant for External OSD Controller
102
O
Horizontal Sync Output meant for External OSD Controller
103
O
Vertical Sync Output meant for External OSD Controller
104
O
Field Signal Output meant for External OSD Controller
86
IO
These Pins provide the Panel Data as shown in the TTL Display Interface Table below.
These are available as General Purpose Input / Output Pins when not used as Panel
87
Data.
88
89
No
I/O
Description
53
O
Panel Bias Control (backlight enable) [Tri-state output, 5V- tolerant]
54
O
Panel Power Control [Tri-state output, 5V- tolerant]
56
DP
Digital Power for LVDS Block. Connect to digital 3.3V supply.
57
O
Reserved. Output for Testing Purpose only at Factory.
58
G
Ground for LVDS outputs.
59
DP
Digital Power for LVDS outputs. Connect to digital 3.3V supply.
60
O
These form the Differential Data Output for Channel – 3 (Even).
61
O
62
O
These form the Differential Clock Output Even Channel.
63
O
64
O
These form the Differential Data Output for Channel – 2 (Even).
65
O
66
O
These form the Differential Data Output for Channel – 1 (Even).
67
O
68
O
These form the Differential Data Output for Channel – 0 (Even).
69
O
70
G
Ground for LVDS outputs.
71
DP
Digital Power for LVDS outputs. Connect to digital 3.3V supply.
72
O
These form the Differential Data Output for Channel – 3 (Odd).
73
O
74
O
These form the Differential Clock Output Odd Channel.
75
O
76
O
These form the Differential Data Output for Channel – 2 (Odd).
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77
O
y
78
O
These form the Differential Data Output for Channel – 1 (Odd).
i
79
O
80
O
These form the Differential Data Output for Channel – 0 (Odd).
81
O
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8
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3
6 7
1 3
1 5
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9 4
2 8
0 5
8
2 9
9 4
2 8
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DTR-7.8
9 9
9 9
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