Dallas Semiconductor MAXIM DS3112 Manuals

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Dallas Semiconductor MAXIM DS3112 Manual (133 pages)

TEMPE T3/E3 Multiplexer 3.3V T3/E3 Framer and M13/E13/G.747 Mux

Brand: Dallas Semiconductor | Category: Multiplexer | Size: 2.44 MB

Table of Contents
2
Detailed Description
7
Applicable Standards
8
Main Ds3112 Tempe Features
9
General Features
9
T3/E3 Framer
9
T2/E2 Framer
9
HDLC Controller
9
FEAC Controller
9
Bert
10
Diagnostics
10
Control Port
10
Packaging and Power
10
Figure 1-1. DS3112 Framer and Multiplexer Block Diagram (T3 Mode)
11
Figure 1-2. DS3112 Framer and Multiplexer Block Diagram (E3 Mode)
12
Figure 1-3. DS3112 Framer and Multiplexer Block Diagram (G.747 Mode)
13
Pin Description
14
Table 2-1. Pin Naming Convention
14
Table 2-2. Pin Description
14
Cpu Bus Signal Description
19
T3/E3 Receive Framer Signal Description
21
Figure 2-1. T3/E3 Receive Framer Timing
22
T3/E3 Transmit Formatter Signal Description
23
Figure 2-2. T3/E3 Transmit Formatter Timing
24
Low-Speed (T1 or E1) Receive Port Signal Description
25
Low-Speed (T1 or E1) Transmit Port Signal Description
26
High-Speed (T3 or E3) Receive Port Signal Description
28
High-Speed (T3 or E3) Transmit Port Signal Description
28
Jtag Signal Description
29
Supply, Test, Reset, and Mode Signal Description
29
Table 2-3. Mode Select Decode
30
Memory Map
31
Table 3-1. Memory Map
31
Master Device Configuration and Status/Interrupt
33
Master Reset and ID Register Description
33
Master Configuration Registers Description
34
Master Status and Interrupt Register Description
38
Status Registers
38
Figure 4-1. Event Status Bit
38
Figure 4-2. Alarm Status Bit
38
Msr
39
Figure 4-3. Real-Time Status Bit
39
Figure 4-4. BERT Status Bit Flow
41
Figure 4-5. HDLC Status Bit Flow
42
Figure 4-6. T2E2SR1 Status Bit Flow
43
Figure 4-7. T2E2SR2 Status Bit Flow
44
Figure 4-8. T1LB Status Bit Flow
44
Figure 4-9. T3E3SR Status Bit Flow
45
Test Register Description
47
T3/E3 Framer
48
T3/E3 Line Loopback
48
T3/E3 Diagnostic Loopback
48
T3/E3 Payload Loopback
48
T3/E3 Framer Control Register Description
49
T3/E3 Framer Status and Interrupt Register Description
53
Figure 5-1. T3E3SR Status Bit Flow
54
Table 5-1. T3 Alarm Criteria
56
Table 5-2. E3 Alarm Criteria
57
T3/E3 Performance Error Counters
59
M13/E13/G.747 Multiplexer and T2/E2/G.747 Frame
62
T1/E1 Ais Generation
62
T2/E2/G.747 Framer Control Register Description
62
T2/E2/G.747 Framer Status and Interrupt Register Description
64
Figure 6-1. T2E2SR1 Status Bit Flow
65
Figure 6-2. T2E2SR2 Status Bit Flow
66
Table 6-1. T2 Alarm Criteria
67
Table 6-2. E2 Alarm Criteria
67
Table 6-3. G.747 Alarm Criteria
67
T1/E1 Ais Generation Control Register Description
68
T1/E1 Loopback and Drop and Insert Functionality
70
T1/E1 Line Loopback
70
T1/E1 Diagnostic Loopback
70
T1 Line Loopback Command
70
T1/E1 Drop and Insert
70
T1/E1 Loopback Control Register Description
71
T1 Line Loopback Command Status Register Description
75
T1/E1 Drop and Insert Control Register Description
76
Figure 7-1. T1LBSR1 and T1LBSR2 Status Bit Flow
76
Bert
78
Bert Register Description
78
Figure 8-1. BERT Status Bit Flow
86
Hdlc Controller
87
Receive Operation
87
Transmit Operation
87
Hdlc Control and Fifo Register Description
88
Hdlc Status and Interrupt Register Description
91
Figure 9-1. HSR Status Bit Flow
94
Feac Controller
96
Feac Control Register Description
96
Feac Status Register Description
98
Jtag
99
Figure 11-1. JTAG Block Diagram
99
Tap Controller State Machine Description
100
Figure 11-2. TAP Controller State Machine
100
Test-Logic-Reset
101
Run-Test-Idle
101
Select-DR-Scan
101
Capture-DR
101
Shift-DR
101
Exit1-DR
101
Pause-DR
101
Exit2-DR
101
Update-DR
101
Select-IR-Scan
101
Capture-IR
102
Shift-IR
102
Exit1-IR
102
Pause-IR
102
Exit2-IR
102
Update-IR
102
Instruction Register and Instructions
103
Sample/Preload
103
Extest
103
Bypass
103
Idcode
103
Highz
103
Table 11-1. Instruction Codes
103
Clamp
104
Test Registers
104
Bypass Register
104
Identification Register
104
Boundary Scan Register
104
Table 11-2. Boundary Scan Control Bits
104
DC Electrical Characteristics
109
Table 12-1. Recommended DC Operating Conditions
109
Table 12-2. DC Characteristics
109
Ac Electrical Characteristics
110
Table 13-1. AC Characteristics-Low-Speed (T1 and E1) Ports
110
Figure 13-1. Low-Speed (T1 and E1) Port AC Timing Diagram
111
Figure 13-2. High-Speed (T3 and E3) Port AC Timing Diagram
112
Table 13-2. AC Characteristics-High-Speed (T3 and E3) Ports
112
Figure 13-3. Framer (T3 and E3) Port AC Timing Diagram
113
Table 13-3. AC Characteristics-Framer (T3 and E3) Ports
113
Table 13-4. AC Characteristics-CPU Bus (Multiplexed and Nonmultiplexed)
114
Figure 13-4. Intel Read Cycle (Nonmultiplexed)
115
Figure 13-5. Intel Write Cycle (Nonmultiplexed)
115
Figure 13-6. Motorola Read Cycle (Nonmultiplexed)
116
Figure 13-7. Motorola Write Cycle (Nonmultiplexed)
116
Figure 13-8. Intel Read Cycle (Multiplexed)
117
Figure 13-9. Intel Write Cycle (Multiplexed)
117
Figure 13-10. Motorola Read Cycle (Multiplexed)
118
Figure 13-11. Motorola Write Cycle (Multiplexed)
118
Figure 13-12. JTAG Test Port Interface AC Timing Diagram
119
Table 13-5. AC Characteristics-JTAG Test Port Interface
119
Figure 13-13. Reset and Manual Error Counter/Insert AC Timing Diagram
120
Table 13-6. AC Characteristics-Reset and Manual Error Counter/Insert Signals
120
Applications and Standards Overview
121
Application Examples
121
Figure 14-1. Channelized T3/E3 Application
121
M13 Basics
122
Figure 14-2. Unchannelized Dual T3/E3 Application
122
Table 14-1. T Carrier Rates
122
T2 Framing Structure
123
M12 Multiplexing
123
Table 14-2. T2 Overhead Bit Assignments
123
Figure 14-3. T2 M-Frame Structure
124
Figure 14-4. T2 Stuff Block Structure
124
T3 Framing Structure
125
M23 Multiplexing
125
Table 14-3. T3 Overhead Bit Assignments
125
C-Bit Parity Mode
126
Table 14-4. C-Bit Assignment for C-Bit Parity Mode
126
Figure 14-5. T3 M-Frame Structure
127
E13 Basics
128
Figure 14-6. T3 Stuff Block Structure
128
Table 14-5. E Carrier Rates
128
E2 Framing Structure and E12 M
129
E3 Framing Structure and G.747 Basics
129
Ultiplexing
129
Figure 14-7. E2 Frame Structure
130
Figure 14-8. E3 Frame Structure
130
Table 14-6. G.747 Carrier Rates
131
Framing Structure and 15 Package Information
132
E12 Multiplexing
132
Figure 14-9. G.747 Frame Structure
132
256-Ball Pbga (56-G6002-001)
133

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