C.2
Sync
Pin Number Connection(s)
1
2
3
4
5
6
7
8
in Section 10.3.
is a word clock with a high level during the left sample and a
FSYNC
low level during the right sample.
rate and
is a master clock with a frequency of 256 or 384 times the sampling
MCK
rate. For sampling rates of 48,000 or 44,100 samples/second, the 256 divider is
used while the 384 divider is used for 32,000 samples/second.
clocks must be provided for the
playback.
Table C.2: Sync Pinout
Direction
+5V
From
DAT-Link
DSPIN
To
DSPOUT
From
READY
Bidirectional
MCK
Bidirectional
SCK
Bidirectional
FSYNC
Bidirectional
Ground
is a serial bit clock at 64 times the sampling
SCK
+ to use an external clock for
DAT-Link
DAT-Link
+
+
DAT-Link
+
All three of these
133
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