Table of Contents
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Pin Assignments
CS485xx Hardware User's Manual
LQFP-48
Pin #
Function 1
(Default)
25
GPIO18
General Purpose Input/Output 1. DAO_MCLK
26
GPIO4
General Purpose Input/Output 1. DAO1_DATA2
27
GPIO3
General Purpose Input/Output 1. DAO1_DATA1
28
VDDD2
Core power supply voltage
29
GPIO5
General Purpose Input/Output 1. XMTA
30
GNDIO3
I/O ground
31
GPIO6
General Purpose Input/Output 1. DAO2_DATA0
32
GPIO7
General Purpose Input/Output 1. HS4
33
GNDD4
Core ground
34
GPIO9
General Purpose Input/Output 1. SCP_MOSI
35
GPIO10
General Purpose Input/Output 1. SCP_MISO
36
GPIO11
General Purpose Input/Output 1. SCP_CLK
37
VDDIO3
I/O power supply voltage
38
GPIO8
General Purpose Input/Output 1. SCP_CS
39
GPIO12
General Purpose Input/Output 1. SCP_IRQ
40
GNDIO4
I/O ground
41
GPIO13
General Purpose Input/Output 1. SCP_BSY
42
VDDD3
Core power supply voltage
43
XTAL_OUT
Buffered Reference Clock
Input/Crystal Oscillator Input
44
XTI
Reference Clock Input/Crystal
Oscillator Input
45
XTO
Crystal Oscillator Output
46
GNDA
PLL ground
47
PLL_REF_RES
Current Reference Output for
PLL. Connect to resistor.
48
VDDA
PLL power.
Table 9-11
shows the names and functions for each pin of the CS48520.
LQFP-48
Pin #
Function 1
(Default)
1
TEST
Test
2
RESET
Active Low Chip Reset
3
DBDA
Debug Data
4
GNDD1
Core ground
5
DBCK
Debug Clock
6
DAI1_LRCLK
PCM Audio Input Sample
Rate (Left/Right) Clock
7
GNDIO1
I/O ground
8
DAI1_SCLK
PCM Audio Input Bit Clock
9
GNDD2
Core ground
10
GPIO16
General Purpose Input/Output 1. DAI1_DATA0
9-19
Table 9-10. Pin Assignments of CS48540 (Continued)
Description of Default
Secondary Functions
Function
2. HS2
2. HS1
2. HS3
2. SCP_SDA
2. EE_CS
Table 9-11. Pin Assignments of CS48520
Description of Default
Secondary Functions
Function
Copyright 2009 Cirrus Logic, Inc.
Description of Secondary Functions
1. Audio Master Clock
1. Digital Audio Output
2. Hardware Strap Mode Select
1. Digital Audio Output
2. Hardware Strap Mode Select
1. S/PDIF Audio Output A
1. Digital Audio Output
2. Hardware Strap Mode Select
1. Hardware Strap Mode Select
1. SPI Mode Master Data Output/Slave Data
Input
1. SPI Mode Master Data Input/Slave Data
Output
2
2. I
C Mode Master/Slave Data IO
2
1. SPI/I
C Control Port Clock
1. SPI Chip Select
1. Serial Control Port Data Ready Interrupt
Request
1. Serial Control Port Input Busy
2. EEPROM Boot Chip Select.
Description of Secondary Functions
1. Digital Audio Input Data
Pullup
Reset
at
Pwr
Type
State
Reset
BiDi
IN
Y
3.3V (5V tol)
BiDi
IN
Y
3.3V (5V tol)
BiDi
IN
Y
3.3V (5V tol)
PWR
1.8V
BiDi
IN
Y
3.3V (5V tol)
PWR
0V
BiDi
IN
Y
3.3V (5V tol)
BiDi
IN
Y
3.3V (5V tol)
PWR
0V
BiDi
IN
Y
3.3V (5V tol)
BiDi/OD
IN
Y
3.3V (5V tol)
BiDi/OD
IN
Y
3.3V (5V tol)
PWR
3.3V
BiDi
IN
Y
3.3V (5V tol)
BiDi/OD
IN
Y
3.3V (5V tol)
PWR
0V
BiDI/OD
IN
Y
3.3V (5V tol)
PWR
1.8V
BiDi
3.3V (5V tol)
ANA
3.3V (5V tol)
ANA
3.3V
PWR
3.3V
ANA
3.3V
PWR
3.3V
Pullup
Reset
at
Pwr
Type
State
Reset
IN
3.3V (5V tol)
IN
3.3V (5V tol)
BiDi
IN
Y
3.3V (5V tol)
PWR
0V
BiDi
IN
Y
3.3V (5V tol)
IN
Y
3.3V (5V tol)
PWR
0V
IN
Y
3.3V (5V tol)
PWR
0V
BiDi
IN
Y
3.3V (5V tol)
DS734UM7
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