I 2 C Messaging; Performing A Serial I C Write; Figure 3-7. Repeated Start Condition With Ack And Nack - Cirrus Logic CS485 Series User Manual

Serial Control Port Configuration
CS485xx Hardware User's Manual
SCP_CLK
SCP_SDA
Write
Read
SCP_CLK
SCP_SDA
Write
Read
2
3.2.2.2 I C Messaging
Messaging to the CS485xx using the I
2
Section 3.2.2 "I C System Bus Description" on page 3-3
2
3-4. Every I C transaction to the CS485xx will involve 4-byte words - for control and application image
download. A detailed description of the serial SPI communication mode is provided in this section. This
includes:
• A flow diagram and description for a serial I
• A flow diagram and description for a serial I
3.2.2.2.1 SCP_BSY Behavior
The SCP_BSY signal is not part of the I
master that it cannot receive any more data. It performs the same function as that of holding SCP_CLK low
to halt transmission. A falling edge of the SCP_BSY signal indicates the master must halt transmission.
Once the SCP_BSY signal goes high, the suspended transaction may continue. It is important for the host to
obey the SCP_BSY pin status for proper communication with the DSP.
3.2.2.3 Performing a Serial I
Information provided in this section is intended as a functional description indicating how to use the
configured serial control port to perform a I
(slave). The system designer must ensure that all timing constraints of the I
CS485xx datasheet for timing specifications). When writing to the CS485xx, the same protocol described in
this section will be used when writing single-word messages to the boot firmware, writing multiple-word
overlay images to the boot firmware, and writing multiple-word messages to application firmware. The
examples given can therefor be expanded to fit any I
The flow diagram shown in
protocol for SCP. This protocol is discussed in the high-level procedure in
3-7
Data Byte
M
S
Data Byte
M
S

Figure 3-7. Repeated Start Condition with ACK and NACK

2
C bus requires usage of all the information provided in the above I
2
C protocol, but it is provided so that the slave can signal to the
2
C Write
2
C write from an external device (master) to the CS485xx DSP
Figure 3-8 below, illustrates the sequence of events that define the I
Copyright 2009 Cirrus Logic, Inc.
Start
A[6] A[5] A[4] A[3]
ACK
S
M
Start
A[6] A[5] A[4] A[3]
NACK
S
M
M = Master Drives SDA
S = Slave Drives SDA
and Section 3.2.2.1 "I
2
C write
2
C read
2
C writing situation.
Section
A[2] A[1] A[0] R/W ACK
M S
M S
A[2] A[1] A[0] R/W ACK
M S
M S
2
C Bus Dynamics" on page
2
C write cycle are met (see the
2
C write
3.2.2.3.1.
DS734UM7
2
C