User Manuals: Cirrus Logic CS4244-DNZ Audio Interface

Manuals and User Guides for Cirrus Logic CS4244-DNZ Audio Interface. We have 1 Cirrus Logic CS4244-DNZ Audio Interface manual available for free PDF download: Manual

Cirrus Logic CS4244-DNZ Manual (63 pages)

4 In/4 Out Audio CODEC with PCM and TDM Interfaces

Brand: Cirrus Logic | Category: Computer Hardware | Size: 2 MB

Table of Contents
2
Pin Descriptions
5
Figure 1.CS4244 Pinout
5
I/O Pin Characteristics
6
Typical Connection Diagram
7
Figure 2.Typical Connection Diagram
7
Characteristics and Specifications
8
Recommended Operating Conditions
8
Absolute Maximum Ratings
8
DC Electrical Characteristics
9
Typical Current Consumption
10
Analog Input Characteristics (Commercial Grade)
11
Analog Input Characteristics (Automotive Grade)
12
Figure 3.Test Circuit for ADC Performance Testing
13
Figure 4.PSRR Test Configuration
13
Adc Digital Filter Characteristics
14
Analog Output Characteristics (Commercial Grade)
15
Analog Output Characteristics (Automotive Grade)
16
Figure 5.Equivalent Output Test Load
16
Combined Dac Interpolation & On-Chip Analog Filter Response
17
Digital I/O Characteristics
18
Switching Characteristics - Serial Audio Interface
19
Figure 6.TDM Serial Audio Interface Timing
20
Figure 7.PCM Serial Audio Interface Timing
20
Switching Specifications - Control Port
21
Figure 8.I²C Control Port Timing
21
Applications
22
Power Supply Decoupling, Grounding, and PCB Layout
22
Recommended Power-Up & Power-Down Sequence
22
Figure 9.System Level Initialization and Power-Up/Down Sequence
23
I²C Control Port
24
Figure 10.DAC DC Loading
24
Figure 11.Timing, I²C Write
25
Figure 12.Timing, I²C Read
25
System Clocking
26
Table 1. Speed Modes
26
Table 2. Common Clock Frequencies
26
Figure 13.Master Mode Clocking
27
Table 3. Master Mode Left Justified and I²S Clock Ratios
27
Table 4. Slave Mode Left Justified and I²S Clock Ratios
27
Table 5. Slave Mode TDM Clock Ratios
27
Serial Port Interface
28
Figure 14.TDM System Clock Format
28
Figure 15.32-Bit Receiver Channel Block
28
Figure 16.Serial Data Coding and Extraction Options Within the TDM Streams
29
Figure 17.Left Justified Format
30
Figure 18.I²S Format
30
Internal Signal Path
31
Figure 19.Audio Path Routing
31
Figure 20.Conventional SDOUT (Left) Vs. Sidechain SDOUT (Right) Configuration
32
Figure 21.DAC1-4 Serial Data Source Selection
33
Figure 22.Example Serial Data Source Selection
34
Figure 23.ADC Path
35
Figure 24.Single-Ended to Differential Active Input Filter
36
Figure 25.Single-Ended to Differential Active Input Filter - DC Coupled Input Signal (VA/2 Centered)
36
Figure 26.DAC1-4 Path
37
Figure 27.De-Emphasis Curve
38
Figure 28.Passive Analog Output Filter
38
Figure 29.Volume Implementation for the DAC1-4 Path
39
Figure 30.Soft Ramp Behavior
40
Table 6. Soft Ramp Rates
41
Table 7. Noise Gate Bit Depth Settings
41
Reset Line
42
Error Reporting and Interrupt Behavior
42
Table 8. Error Reporting and Interrupt Behavior Details
42
Figure 31.Interrupt Behavior and Example Interrupt Service Routine
44
Register Quick Reference
45
Register Descriptions
47
Device I.D. A-F (Address 01H-03H) (Read Only)
47
Revision I.D. (Address 05H) (Read Only)
47
Clock & SP Select (Address 06H)
48
Sample Width Select (Address 07H)
49
Serial Port Control (Address 08H)
49
Serial Port Data Select (Address 09H)
50
ADC Control 1 (Address 0Fh)
51
ADC Control 2 (Address 10H)
51
DAC Control 1 (Address 12H)
52
DAC Control 2 (Address 13H)
52
DAC Control 3 (Address 14H)
53
DAC Control 4 (Address 15H)
53
Volume Mode (Address 16H)
54
Master and DAC1-4 Volume Control (Address 17H, 18H, 19H, 1Ah, & 1Bh)
55
Interrupt Control (Address 1Eh)
55
Interrupt Mask 1 (Address 1Fh)
56
Interrupt Mask 2 (Address 20H)
57
Interrupt Notification 1 (Address 21H) (Read Only)
57
Interrupt Notification 2 (Address 22H) (Read Only)
58
Adc Filter Plots
59
Figure 32.ADC Stopband Rejection
59
Figure 33.ADC Transition Band
59
Figure 34.ADC Transition Band (Detail)
59
Figure 35.ADC Passband Ripple
59
Figure 36.ADC HPF (48 Khz)
59
Figure 37.ADC HPF (96 Khz)
59
Dac Filter Plots
60
Figure 38.SSM DAC Stopband Rejection
60
Figure 39.SSM DAC Transition Band
60
Figure 40.SSM DAC Transition Band (Detail)
60
Figure 41.SSM DAC Passband Ripple
60
Figure 42.DSM DAC Stopband Rejection
61
Figure 43.DSM DAC Transition Band
61
Figure 44.DSM DAC Transition Band (Detail)
61
Figure 45.DSM DAC Passband Ripple
61
Package Dimensions
62
Figure 46.Package Drawing
62
10.Ordering Information
63
11.Revision History
63

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Cirrus Logic CS4244-DNZ Manual (63 pages)

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