Cirrus Logic CS485 Series User Manual page 44

Start
SCP_CLK
SCP_SDA 7-bit Address
M
2
Note: The I C slave is always responsible for driving the ACK for the address byte.
Start
SCP_CLK
SCP_SDA 7-bit Address
SCP_IRQ
M
2
Notes: 1.The I C slave is drives the ACK for the address byte.
2
2.The I C master is responsible for controlling ACK during I
providing ACK.
3.SCP_IRQ remains low until the rising edge of the clock for the last bit of the last byte read from the I
4.A NACK is sent by the master after the last byte to indicate the end of the read cycle. This must be followed with an I
2
I C Repeated-Start condition.
Data Byte 3 (MSB) Data Byte 2
S M S
Figure 3-10. Sample Waveform for I
Data Byte 3 (MSB)
S S M
Figure 3-11. Sample Waveform for I
2
C reads. In general, the receiver in an I
Data Byte 1
M S M
2
C Write Functional TIming
Data Byte 2 Data Byte 1
S M S
M = Master Drives SDA
S = Slave Drives SDA
2
C Read Functional Timing
Stop
Data Byte 0 (LSB)
S M S M
Stop
Data Byte 0 (LSB)
M S M M
2
C transaction is responsible for
2
C slave.
2
C Stop condition or