Table of Contents
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LQFP-48
Pin #
Function 1
(Default)
36
GPIO11
General Purpose Input/Output 1. SCP_CLK
37
VDDIO3
I/O power supply voltage
38
GPIO8
General Purpose Input/Output 1. SCP_CS
39
GPIO12
General Purpose Input/Output 1. SCP_IRQ
40
GNDIO4
I/O ground
41
GPIO13
General Purpose Input/Output 1. SCP_BSY
42
VDDD3
Core power supply voltage
43
XTAL_OUT
Buffered Reference Clock
Input/Crystal Oscillator Input
44
XTI
Reference Clock Input/Crystal
Oscillator Input
45
XTO
Crystal Oscillator Output
46
GNDA
PLL ground
47
PLL_REF_RES
Current Reference Output for
PLL. Connect to resistor.
48
VDDA
PLL power.
Table 9-10
shows the names and functions for each pin of the CS48540.
LQFP-48
Pin #
Function 1
(Default)
1
TEST
Test
2
RESET
Active Low Chip Reset
3
DBDA
Debug Data
4
GNDD1
Core ground
5
DBCK
Debug Clock
6
DAI1_LRCLK
PCM Audio Input Sample
Rate (Left/Right) Clock
7
GNDIO1
I/O ground
8
DAI1_SCLK
PCM Audio Input Bit Clock
9
GNDD2
Core ground
10
GPIO16
General Purpose Input/Output 1. DAI1_DATA0
11
GPIO0
General Purpose Input/Output 1. DAI1_DATA1
12
VDDIO1
I/O power supply voltage
13
GPIO1
General Purpose Input/Output 1. DAI1_DATA2
14
GPIO2
General Purpose Input/Output
15
GPIO17
General Purpose Input/Output 1. DAI2_DATA0
16
VDDD1
Core power supply voltage
17
GPIO14
General Purpose Input/Output 1. DAI2_LRCLK
18
GPIO15
General Purpose Input/Output 1. DAI2_SCLK
19
GNDIO2
I/O ground
20
DAO1_DATA0
Digital Audio Output 0
21
DAO_LRCLK
PCM Audio Sample Rate
Clock
22
GNDD3
Core ground
23
DAO_SCLK
PCM Audio Output Bit Clock
24
VDDIO2
I/O power supply voltage
DS734UM7
Table 9-9. Pin Assignments of CS48560 (Continued)
Description of Default
Secondary Functions
Function
2. EE_CS
Table 9-10. Pin Assignments of CS48540
Description of Default
Secondary Functions
Function
1. HS0
Copyright 2009 Cirrus Logic, Inc.
Description of Secondary Functions
2
1. SPI/I
C Control Port Clock
1. SPI Chip Select
1. Serial Control Port Data Ready Interrupt
Request
1. Serial Control Port Input Busy
2. EEPROM Boot Chip Select.
Description of Secondary Functions
1. Digital Audio Input Data
1. Digital Audio Input Data
1. Digital Audio Input Data
1. Digital Audio Input Data
1. PCM Audio Input Sample Rate (Left/
Right) Clock
PCM Audio Input Bit Clock
1. Hardware Strap Mode Select.
Pin Assignments
CS485xx Hardware User's Manual
Pullup
Reset
at
Pwr
Type
State
Reset
BiDi/OD
IN
Y
3.3V (5V tol)
PWR
3.3V
BiDi
IN
Y
3.3V (5V tol)
BiDi/OD
IN
Y
3.3V (5V tol)
PWR
0V
BiDI/OD
IN
Y
3.3V (5V tol)
PWR
1.8V
BiDi
3.3V (5V tol)
ANA
3.3V (5V tol)
ANA
3.3V
PWR
3.3V
ANA
3.3V
PWR
3.3V
Pullup
Reset
at
Pwr
Type
State
Reset
IN
3.3V (5V tol)
IN
3.3V (5V tol)
BiDi
IN
Y
3.3V (5V tol)
PWR
0V
BiDi
IN
Y
3.3V (5V tol)
IN
Y
3.3V (5V tol)
PWR
0V
IN
Y
3.3V (5V tol)
PWR
0V
BiDi
IN
Y
3.3V (5V tol)
BiDi
IN
Y
3.3V (5V tol)
PWR
3.3V
BiDi
IN
Y
3.3V (5V tol)
BiDi
IN
Y
3.3V (5V tol)
BiDi
IN
Y
3.3V (5V tol)
PWR
1.8V
BiDi/OD
IN
Y
3.3V (5V tol)
BiDi
IN
Y
3.3V (5V tol)
PWR
0V
BiDi
IN
3.3V (5V tol)
BiDi
IN
Y
3.3V (5V tol)
PWR
0V
BiDi
IN
Y
3.3V (5V tol)
PWR
3.3V
9-18
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