Cirrus Logic CS485 Series User Manual page 77

System Clocking Controls
CS485xx Hardware User's Manual
7.1 System Clocking Controls
The CS485xx incorporates one programmable phase locked loop (PLL) clock synthesizer. The PLL take an
input reference clock and produces all the clocks required to run the DSP and peripherals.
The input reference clock may come from an external 24.576 MHz oscillator connected to the XTI pin. In this
case the XTO pin should be left disconnected. This is the preferred source in A/V Receiver designs that
require low-jitter clocks.
The built in crystal oscillator circuit may be used to generate the reference clock for the PLLs. A parallel
resonant-type crystal is connected between the XTI and XTO pins as shown in
is specific to each crystal. The CS485xx Data Sheet specifies acceptable crystal parameters (including C
and ESR).
When a crystal is used, XTAL_OUT may be used to clock other devices in the system such as an external S/
PDIF receiver.
Table 7-1 describes the XTAL_OUT, XTI, and XTO pins.
LQFP-100
Pin #
43
44
45
The PLL is controlled by the clock manager in the DSP O/S application software. AN298, CS485xx Firmware
User's Manual should be referenced regarding what CLKIN input frequency and PLL multiplier values are
supported.
Figure 7-1 shows the schematic of the CS485xx crystal oscillator.
7-1
Crystal Oscillator and System Clocking
Table 7-1. DSP Core Clock Pins
Pin
Pin Name
Type
XTAL_OUT Output
XTI Input
XTO Output
Copyright 2008 Cirrus Logic, Inc.
Figure
Pin Description
Buffered version of XTI. Can be programmed
to be Fxtal / 2.
Reference Clock Input/Crystal Oscillator Input.
An external clock may be input directly to this
pin or one end of a crystal may be connected
to this pin.
Crystal Oscillator Output. One end of a crystal
oscillator is connected to this pin. This pin
cannot be used to drive external circuitry.
Chapter 7
7-1. The value of C1
L
DS734UM7