Figure 6-1. Cs48560 Dao Block Diagram - Cirrus Logic CS485 Series User Manual

32-bit audio dsp family

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DAO_MCLK is the master clock and is firmware configurable to be either an input (slave) or an output

(master). If MCLK is to be used as an output, the internal PLL must be used. As an output MCLK can be

configured to provide a 128Fs, 256Fs, or 512Fs clock, where Fs is the output sample rate.

• DAO_SCLK is the bit clock used to clock data out on DAOn_DATA[n].

• DAO_LRCLK is the data framing clock whose frequency is equal to the sampling frequency for the

DAO data outputs.

• DAOn_DATA[n] are the data outputs and are typically configured for outputting two channels of I

or left-justified PCM data.

DS734UM7

DAO1_DATA0

DAO1_DATA1

DAO1_DATA2

DAO1_DATA3

DAO2_DATA0

DAO2_DATA1

DAO_MCLK

DAO_SCLK

DAO_LRCLK

Figure 6-1. CS48560 DAO Block Diagram

Digital Audio Output Port Description

CS485xx Hardware User's Manual

DAO1_DATA3, XMTA

SPDIF

ENCODER

6-2

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