Ground; Decoupling; Pll Filter; Analog Power Conditioning - Cirrus Logic CS485 Series User Manual

Pin Description
CS485xx Hardware User's Manual

9.2.1.2 Ground

For two-layer circuit boards, care should be taken to have sufficient grounding between the DSP and parts in
which it will be interfacing (DACs, ADCs, S/PDIF Receivers, microcontrollers, and especially external
memory). Insufficient grounding can degrade noise margins between devices resulting in data integrity
problems.
LQFP-48
Pin #
4
9
22
33
7
19
30
40

9.2.1.3 Decoupling

It is necessary to decouple the power supply by placing capacitors directly between the power and ground of
the CS485xx. Each pair of power/ground pins (VDD1/GND1, etc.) should have its own decoupling capacitor.
The recommended procedure is to place a 0.1 uF capacitor as close as physically possible to each power
pin connected with a wide, low-inductance trace. A bulk capacitor of at least 10 uF is recommended for each
power plane.

9.2.2 PLL Filter

9.2.2.1 Analog Power Conditioning

In order to obtain the best performance from the CS485xx internal PLL, the analog power supply VDDA
must be as noise free as possible. A ferrite bead and two capacitors should be used to filter the VDDIO to
generate VDDA. This power scheme is shown in the Typical Connection diagrams.
LQFP-48
Pin #
48
46
9-11
Table 9-3. Core and I/O Ground Pins
Pin Name Pin Type
GND1
GND2
GND3
GND4
GNDIO1
GNDIO2
GNDIO3
GNDIO4
Table 9-4. PLL Supply Pins
Pin Name Pin Type
VDDA Input
GNDA Input
Copyright 2009 Cirrus Logic, Inc.
Pin Description
Core Ground.
Input
I/O Ground
Pin Description
PLL supply. This voltage must be 3.3V. This
must be clean, noise-free analog power.
PLL ground. This ground should be as noise-
free as possible.
DS734UM7