Operational Mode Selection; Slave Boot Procedures; Table 2-1. Operation Modes - Cirrus Logic CS485 Series User Manual

2.2 Operational Mode Selection

The operational mode for the CS485xx is selected by the values of the HS[4:0] pins on the rising edge of
RESET. This value determines the communication mode used until the part is reset again. This value also
determines the method for loading application code. The table below shows the different operational modes
and the HS[4:0] values for each mode.
HS[4:0]
X 0 0 0
X 1 0 0
X 0 0 0
X 1 0 0
X 0 0 1
X 1 0 1
X X 1 0
X X 1 0
X X 1 1
X X 1 1
X X 0 1
2
a. In I C master mode, the Image Start address (0x0) is sent as a 16-bit value, with the default I
address of 0x50, I
b. SPI master mode 1 is to support the legacy 16-bit SPI EEPROM. The following defaults are used: SPI
Command Byte 0x03, Image Start address 0x0 is sent as a 16-bit value, no dummy bytes, SPI clock
frequency = F
c. In SPI Master mode 2, the following defaults are used: SPI Command Byte 0x68, Image Start address
0x0 is sent as a 24-bit value, 4 dummy bytes sent following the address (and before reading image
data), SPI clock frequency = Fdclk / 2. This mode supports the Atmel
d. In SPI Master mode 3, the following defaults are used: SPI command byte 0x03, Image Start address
0x0 is sent as a 24-bit value, no dummy bytes, SPI clock frequency = F
ST SPI EEPROM devices.
e. For all SPI Master boot modes, by default GPIO13 is used as EE_CS.
f. For Flash Master modes, the following defaults are used: clock ratio=1:1, Endian Mode = little-endian,
Chip Select polarity = active-low, 0-cycle delay from CS Address Change to Output Enable, 4-cycle
delay from CS to Read Access.
g. F is specified in the CS485xx Data Sheet.
dclk

2.3 Slave Boot Procedures

When the
CS485xx
follow an outlined procedure for correctly loading application code. The slave boot procedure is described in
this section. Slave boot requires the system host controller to send messages to, and read back messages
from, the . These messages have been outlined in
CS485xx
The has different.uld files (overlays) for certain processing tasks. Slave booting the
CS485xx
requires loading multiple overlays - differing from previous Cirrus Logic Audio DSP families (that is,
CS493xx, CS494xxx). Please refer to AN298, "
information on the breakdown of processing tasks for each overlay.
DS734UM7

Table 2-1. Operation Modes

Mode
2 a
0
Master I C
b
0
Master SPI 1
c
1
Master SPI 2
d
1
Master SPI 3
0 RESERVED
0 RESERVED
2
0
Slave I C
1 Slave SPI
0 RESERVED
1 RESERVED
1 RESERVED
2
C clock frequency = F
/ 4.
dclk
is the slave boot device, the system host controller (as the master boot device) must
Copyright 2009 Cirrus Logic, Inc.
Boot Master
Device
CS485xx
CS485xx
CS485xx
CS485xx
System Host
System Host
dclk
/ 72.
Section 2.3.3 "Boot Messages" on page
Firmware User's Manual" regarding more
CS485xx
Operational Mode Selection
CS485xxr Hardware User's Manual
Boot Slave Device
2
I C External ROM
SPI (Mode 1) External ROM
SPI (Mode 2) External ROM
SPI (Mode 3) External ROM
CS485xx
CS485xx
2
C
®
SPI Flash memory.
/ 2. This mode supports the
dclk
CS485xx
5, 6, 7
5, 6, 7
e, f,g
2-6.
2-2