Figure 1-3. Cs48520 Chip Functional Block Diagram - Cirrus Logic CS485 Series User Manual

Figure 1-3 illustrates the functional block diagram for CS48520.
SRAM
ROM
SRAM
ROM
SRAM
ROM
See AN298, CS485xx Firmware User's Manual for a list the firmware modules that are available on
CS485xx DSPs.
The audio processing algorithms, post-processing application codes, and/or Cirrus Framework
and the associated application notes are available through the Cirrus Software Licensing Program. Standard
post-processing code modules are only available to customers who qualify for the Cirrus Framework™
CS485xx Family DSP Programming Kit. Please refer to the Related Documents section of this manual for
additional application note information.
The CS485xx supports master-mode interface on the serial control port to interface to SPI™ and I
FLASH chips, thus allowing products to be field upgraded as new audio algorithms are developed.
DS734UM7
CS48520
Peripheral
Debug
Controller
X
Ext (64 bit)
Log/Exp
Security
Y
32-bit Dual Datapath
X
DSP
P
with 72-bit
Y
Accumulators
Decryptor
P
Programmable
Interrupt Controller
DMA Controller with 8 Channels
Peripheral Bus

Figure 1-3. CS48520 Chip Functional Block Diagram

Copyright 2009 Cirrus Logic, Inc.
DAI1
DAI
Bus
Controller
Controller
DAI2
DAI
Controller
DAO1
64 bit
DAO
Controller
DAO2
DMA Bus
CS485xx Hardware User's Manual
Stereo Audio Input/DSD
Stereo Audio Input
Stereo Audio Output
SPDIF Transmitter
Stereo Audio Output
Serial Control Port
Timers
GPIOs
Clock Manager and PLL
™
modules
2
C
Overview
®
serial
1-4