Spi Bus Dynamics; Figure 3-13. Block Diagram Of Spi System Bus - Cirrus Logic CS485 Series User Manual

SPI Port
CS485xx Hardware User's Manual
Both modes of the CS485xx serial port are shown in

3.3.1.1 SPI Bus Dynamics

A SPI transaction begins by the master driving the slave chip select SCP_CS low. SPI transactions end by
the master driving the SCP_CS high. This SPI bus is considered busy while any device's SCP_CS signal is
low. The bus is free only when all slave SCP_CS signals are high. A high-to-low transition on the SCP_CS
line defines an SPI Start condition. A low-to-high transition on the SCP_CS line defines an SPI Stop
condition. Start and Stop conditions are always generated by the master. The bus is considered to be busy
after the Start condition. The bus is considered to be free again following the Stop condition.
The data bits of the SCP_MOSI and SCP_MISO line are valid on the rising edge of SCP_CLK. It is the
slave's responsibility to accept or supply bytes on the bus at the rate at which the master is driving
SCP_CLK.
All data put on the SCP_MOSI and SCP_MISO lines must be in 8-bit bytes. The number of bytes that can be
transmitted per transfer is unrestricted. Data is transferred with the most-significant bit (MSB) first. For the
CS485xx slave SPI port, the first byte is an address byte that must always be sent by the master after a Start
condition. This address byte is an "I
is 1000000b (0x80).
If the SPI transaction is a write from master to the CS485xx (R/W = 0, Address = 0x80), then the master will
clock the SCP_CLK signal and drive the SCP_MOSI signal with data bytes for the to read. If the SPI
transaction is a read to the master from the CS485xx (R/W = 1, Address = 0x81), then the master will drive
the SCP_CLK signal and read the SCP_MISO signal with the data bytes from the CS485xx.
3-15
3.3k
System Microcontroller
GPIO
GPIO
SCK
MOSI
MISO
GPIO
GPIO
SPI EEPROM
MOSI
MISO
CS
CLK

Figure 3-13. Block Diagram of SPI System Bus

2
C-type" command of a 7-bit address + a R/W bit. The 7-bit SPI address
Copyright 2009 Cirrus Logic, Inc.
Figure 3-13.
3.3V
3.3k
CS485xx
RESET
SCP_CS
SCP_CLK
SLAVE
SCP_MOSI
ONLY
SCP_MISO
SCP_IRQ
SCP_BSY
CS485xx
MASTER
SCP_MOSI
SCP_MISO
ONLY
SCP_CS
SCP_CLK
DS734UM7