Intel 81342 Developer's Manual page 595

D D R S D R A M M e m o r y C o n t r o l l e r — I n t e l
1 0 . A f t e r w a i t i n g T
o n e o f t h e f o l l o w i n g o p t i o n s t o S D I R t o p r o g r a m D D R S D R A M p a r a m e t e r s a n d t o
R e s e t
— 0 0 0 2 _ 9 9 0 0 H f o r C A S L a t e n c y = 3 a n d W r i t e R e c o v e r y = 3 , o r
— 0 0 0 3 _ 9 9 0 0 H f o r C A S L a t e n c y = 3 a n d W r i t e R e c o v e r y = 4 , o r
— 0 0 0 2 _ A 1 0 0 H f o r C A S L a t e n c y = 4 a n d W r i t e R e c o v e r y = 3 , o r
— 0 0 0 3 _ A 1 0 0 H f o r C A S L a t e n c y = 4 a n d W r i t e R e c o v e r y = 4 , o r
— 0 0 0 2 _ A 9 0 0 H f o r C A S L a t e n c y = 5 a n d W r i t e R e c o v e r y = 3 , o r
— 0 0 0 3 _ A 9 0 0 H f o r C A S L a t e n c y = 5 a n d W r i t e R e c o v e r y = 4
T h e D M C U s u p p o r t s t h e f o l l o w i n g D D R S D R A M m o d e p a r a m e t e r s :
a. CAS Latency (tCAS) = 3, 4, or 5 for DDR2 based on the programmed setting in
Control Register 0 —
b. Burst Type = Sequential
c. Burst Length (BL) = four
F i g u r e 8 7 . S u p p o r t e d D D R S D R A M M o d e R e g i s t e r S e t t i n g s
T h e D D R S D R A M m o d e
r e g i s t e r r e s i d e s i n t h e
D D R S D R A M d e v i c e s .
N o t e : B A [ 1 : 0 ] m u s t b e 0 0
1 1 . A f t e r w a i t i n g T
D D R S D R A M i n t e r f a c e b y s e t t i n g t h e S D I R t o 0 0 0 2 _ 0 0 2 0 H .
1 2 . A f t e r w a i t i n g T
b y s e t t i n g S D I R t o 0 0 0 0 _ 0 0 1 0 H , t h e n e n s u r e a t l e a s t T
a u t o - r e f r e s h
1 3 . A f t e r t h e s e c o n d
s o f t w a r e i s s u e s a
o p t i o n s t o t h e S D I R t o p r o g r a m D D R S D R A M p a r a m e t e r s
— 0 0 0 2 _ 1 9 0 0 H f o r C A S L a t e n c y = 3 a n d W r i t e R e c o v e r y = 3 , o r
— 0 0 0 3 _ 1 9 0 0 H f o r C A S L a t e n c y = 3 a n d W r i t e R e c o v e r y = 4 , o r
— 0 0 0 2 _ 2 1 0 0 H f o r C A S L a t e n c y = 4 a n d W r i t e R e c o v e r y = 3 , o r
— 0 0 0 3 _ 2 1 0 0 H f o r C A S L a t e n c y = 4 a n d W r i t e R e c o v e r y = 4 , o r
— 0 0 0 2 _ 2 9 0 0 H f o r C A S L a t e n c y = 5 a n d W r i t e R e c o v e r y = 3 , o r
— 0 0 0 3 _ 2 9 0 0 H f o r C A S L a t e n c y = 5 a n d W r i t e R e c o v e r y = 4
1 4 . D M C U m a y i s s u e a
c o m m a n d .
1 5 . S o f t w a r e r e - e n a b l e s t h e r e f r e s h c o u n t e r b y s e t t i n g t h e R F R t o t h e r e q u i r e d v a l u e .
D e c e m b e r 2 0 0 7
O r d e r N u m b e r : 3 1 5 0 3 7 - 0 0 2 U S
®
8 1 3 4 1 a n d 8 1 3 4 2
c y c l e s , s o f t w a r e i s s u e s a
m r d
D L L :
SDCR0". Note, when ODT is enabled CAS Latency must be => 4.
A 1 2
0 0 0
O p e r a t i n g M o d e ( A 8 : A 7 ) :
0 0 : N o r m a l O p e r a t i o n ( D o n o t R e s e t D L L )
1 0 : N o r m a l O p e r a t i o n ( I n D L L R e s e t )
O t h e r : X
t o s e l e c t t h e M o d e R e g i s t e r .
2
c y c l e s , s o f t w a r e i s s u e s a
m r d
c y c l e s , s o f t w a r e p r o v i d e s t w o
r p
c o m m a n d .
a u t o - r e f r e s h
m o d e - r e g i s t e r - s e t
row-activate
mode-register-set
A 6
0
B u r s t T y p e :
C A S L a t e n c y :
0 1 0 : 2 ( D D R o n l y )
0 1 1 : 3 ( D D R 2 o n l y )
1 0 0 : 4 ( D D R 2 o n l y )
1 1 0 : 2 . 5 ( D D R o n l y )
O t h e r : X
p r e c h a r g e - a l l
a u t o - r e f r e s h
c y c l e , s o f t w a r e m u s t w a i t T
c o m m a n d b y w r i t i n g o n e o f t h e f o l l o w i n g
c o m m a n d T c y c l e s a f t e r
m r d
I n t e l
c o m m a n d b y w r i t i n g
"SDRAM
A 3 A 0
B u r s t L e n g t h :
0 1 0 : 4
0 : S e q u e n t i a l
B 6 2 6 1 - 0 1
c o m m a n d t o t h e
c y c l e s , a c c o m p l i s h e d
c y c l e s b e t w e e n e a c h
r f c
c y c l e s . T h e n ,
r f c
w i t h o u t
r e s e t t i n g D L L :
mode-register-set
®
8 1 3 4 1 a n d 8 1 3 4 2 I / O P r o c e s s o r s
D e v e l o p e r ' s M a n u a l
5 9 5