Intel 81342 Developer's Manual page 671

D D R S D R A M M e m o r y C o n t r o l l e r — I n t e l
/* Write DLLRCVER Register */
*MCU_DLLRCVER = ((1<<17) | (1<<18) | treg | (coarse << 8) | fine);
/* Read register again to guarantee previous write operation */
*MCU_DLLRCVER;
/* Read a DDR SDRAM Memory Location, this memory read causes
the auto calibration circuit to sample the DQS signal */
val = *ddr_mem_addr;
/* If not defined as a stronly ordered memory region, may need to
put a dependancy here to ensure load from DDR completes */
asm volatile("mov %0, %0" : : "r" (val));
/* Read DLLRCVER register bit 24 to get DQS sample */
val = *MCU_DLLRCVER & (1<<24);
return (val == 0 ? val : 1);
} // End sample_dqs() procedure
D e c e m b e r 2 0 0 7
O r d e r N u m b e r : 3 1 5 0 3 7 - 0 0 2 U S
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I n t e l 8 1 3 4 1 a n d 8 1 3 4 2 I / O P r o c e s s o r s
D e v e l o p e r ' s M a n u a l
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