Intel 81342 Developer's Manual page 670

/* Compute Optimum DLLRCVER Value by moving DLLRCVEREN delay back
by MCLK/4 to be in the pre-ample window */
dllrcver_value -= 16;
/* Make sure we don't go below zero */
if(dllrcver_value < 0)
dllrcver_value = 0;
/* Write new DLLRCVER value */
treg = *MCU_DLLRCVER & (1<<16);
fine = (dllrcver_value & 0x1f);
coarse = ((dllrcver_value >> 5) & 0x7);
*MCU_DLLRCVER = ( treg | (coarse << 8) | fine );
/* Reset the MCU FIFOs */
sdcr0_val = *(MCU_SDCR0);
*(MCU_SDCR0) = sdcr0_val &~ (1<<7); /* Clear Reset FIFO bit */
*(MCU_SDCR0) = sdcr0_val |
return 0;
} // End Algorithm
/* Sample DQS Procedure */
sample_dqs(dllval)
{
unsigned int treg, fine, coarse, val;
volatile unsigned int *ddr_mem_addr = 0;
treg = *MCU_DLLRCVER & (1<<16);
fine = (dllval & 0x1f);
coarse = ((dllval >> 5) & 0x7);
®
I n t e l 8 1 3 4 1 a n d 8 1 3 4 2 I / O P r o c e s s o r s
D e v e l o p e r ' s M a n u a l
6 7 0
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I n t e l 8 1 3 4 1 a n d 8 1 3 4 2 — D D R S D R A M M e m o r y C o n t r o l l e r
(1<<7); /* Set Reset FIFO bit */
/* Pick a DDR addr */
D e c e m b e r 2 0 0 7
O r d e r N u m b e r : 3 1 5 0 3 7 - 0 0 2 U S