Intel 81342 Developer's Manual page 891

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U A R T s — I n t e l
8 1 3 4 1 a n d 8 1 3 4 2
1 5 . 4 . 3
U A R T x I n t e r r u p t E n a b l e R e g i s t e r
T h i s r e g i s t e r e n a b l e s s i x t y p e s o f i n t e r r u p t s w h i c h s e t a v a l u e i n t h e I n t e r r u p t
I d e n t i f i c a t i o n r e g i s t e r . E a c h o f t h e s i x i n t e r r u p t t y p e s c a n b e d i s a b l e d b y c l e a r i n g t h e
a p p r o p r i a t e b i t o f t h e I E R r e g i s t e r . S i m i l a r l y , b y s e t t i n g t h e a p p r o p r i a t e b i t s , s e l e c t e d
i n t e r r u p t s c a n b e e n a b l e d .
T h i s r e g i s t e r a l s o h a s t h e c o n t r o l b i t s o f t h e u n i t e n a b l e a n d N R Z c o d i n g e n a b l e . T h e
u s e o f b i t 7 t o b i t 4 i s d i f f e r e n t f r o m t h e r e g i s t e r d e f i n i t i o n o f s t a n d a r d 1 6 5 5 0 .
N o t e :
A g l o b a l i n t e r r u p t e n a b l e / d i s a b l e e x i s t s i n t h e M o d e m C o n t r o l R e g i s t e r b i t 3 ( I E ) . A f t e r
r e s e t , t h i s b i t m u s t b e s e t o r n o i n t e r r u p t s o c c u r s , r e g a r d l e s s o f t h e s t a t e o f t h e I E R
b i t s . S e e
T a b l e 5 6 6 . U A R T x I n t e r r u p t E n a b l e R e g i s t e r - ( U x I E R )
e s
3 1
u t
P
r v
i b
I O
t r
A t
s
t e
I
b u
P C
n a
r i
t t
A
U n i t #
0
1
B i t
31:8
7
6
5
4
3
2
1
0
D e c e m b e r 2 0 0 7
O r d e r N u m b e r : 3 1 5 0 3 7 - 0 0 2 U S
S e c t i o n 1 5 . 4 . 7 , " U A R T x M o d e m C o n t r o l R e g i s t e r " o n p a g e 8 9 8
2 8
2 4
r v
r v
r v
r v
r v
r v
r v
r v
r v
r v
n a
n a
n a
n a
n a
n a
n a
n a
n a
n a
®
I n t e l X S c a l e
C o r e i n t e r n a l b u s a d d r e s s
+ 2 3 0 4 H ( D L A B = x )
+ 2 3 4 4 H ( D L A B = x )
D e f a u l t
00 0000h
Reserved
0
Preserved
2
UART Unit Enable (UUE):
0
2
0 = t h e u n i t i s d i s a b l e d
1 = t h e u n i t i s e n a b l e d
NRZ coding Enable (NRZE):
0
0 = NRZ coding disabled
2
1 = NRZ coding enabled
Receiver Time Out Interrupt Enable: (RTOIE)
0
0 = Receiver data Time out Interrupt disabled
2
1 = Receiver data Time out Interrupt enabled
Modem Interrupt Enable (MIE):
0
0 = Modem Status interrupt disabled
2
1 = Modem Status interrupt enabled
Receiver Line Status Interrupt Enable (RLSE):
0
0 = Receiver Line Status interrupt disabled
2
1 = Receiver Line Status interrupt enabled
Transmit Data request Interrupt Enable (TIE):
0
0 = Transmit FIFO Data Request interrupt disabled
2
1 = Transmit FIFO Data Request interrupt enabled
Receiver Data Available Interrupt Enable (RAVIE):
0
0 = Receiver Data Available (Trigger level reached) interrupt disabled
2
1 = Receiver Data Available (Trigger level reached) interrupt enabled
2 0
1 6
1 2
r v
r v
r v
r v
r v
r v
r v
r v
r v
r v
n a
n a
n a
n a
n a
n a
n a
n a
n a
n a
A t t r i b u t e L e g e n d :
R V = R e s e r v e d
P R = P r e s e r v e d
R S = R e a d / S e t
D e s c r i p t i o n
I n t e l
.
8
4
r v
r v
r v
p r
r w
r w
r w
r w
r w
r w
n a
n a
n a
n a
n a
n a
n a
n a
n a
n a
R W = R e a d / W r i t e
R C = R e a d C l e a r
R O = R e a d O n l y
N A = N o t A c c e s s i b l e
®
8 1 3 4 1 a n d 8 1 3 4 2 I / O P r o c e s s o r s
D e v e l o p e r ' s M a n u a l
0
r w
n a
8 9 1

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