Intel 81342 Developer's Manual page 859

I n t e r - P r o c e s s o r M e s s a g i n g U n i t — I n t e l
1 3 . 6 . 3 7 . 1 E n d i a n M o d e S u p p o r t
W h e n a c c e s s i n g t h e t e s t a n d s e t r e g i s t e r a r r a y , t h e I M U a l l o w s a n y o f t h e I n t e l X S c a l e
p r o c e s s o r s , r e g a r d l e s s o f t h e i r e n d i a n m o d e s e t t i n g s , t o a c c e s s t h e s a m e d a t a b y t e .
N o t e t h a t i n l i t t l e e n d i a n m o d e , t h e I n t e l X S c a l e
o n t h e l e a s t s i g n i f i c a n t b y t e l a n e o f t h e i n t e r n a l d a t a b u s ( i . e . , b y t e l a n e 0 p e r 3 2 - b i t
b u s ) , a n d i n b i g e n d i a n m o d e t h e I n t e l X S c a l e
t h e m o s t s i g n i f i c a n t b y t e l a n e o f t h e i n t e r n a l d a t a b u s ( i . e . , b y t e l a n e 3 o f p e r 3 2 - b i t
b u s ) .
T h e t e s t a n d s e t r e g i s t e r a r r a y i s o r g a n i z e d i n l i t t l e e n d i a n o r d e r i n t h e I M U r e g a r d l e s s
o f t h e I n t e l X S c a l e
i s b e i n g a c c e s s e d b y a n I n t e l X S c a l e
s e t t i n g o f t h a t p a r t i c u l a r c o r e . I f t h e I n t e l X S c a l e
m o d e , t h e I M U w o u l d d y n a m i c a l l y b y t e - s w a p t h e a l i g n e d D W O R D w i t h i n w h i c h t h e d a t a
b y t e i s c o n t a i n e d . R e f e r t o
r u n n i n g i n l i t t l e e n d i a n m o d e , t h e I M U w o u l d s i m p l y k e e p t h e b y t e s i n t h e i r r e s p e c t i v e
b y t e l a n e s . R e f e r t o
F i g u r e 1 2 0 . I M U h a n d l i n g I n t e l X S c a l e
F i g u r e 1 2 1 . I M U h a n d l i n g I n t e l X S c a l e
Byte Address 3
Byte Address 3
D e c e m b e r 2 0 0 7
O r d e r N u m b e r : 3 1 5 0 3 7 - 0 0 2 U S
®
8 1 3 4 1 a n d 8 1 3 4 2
®
p r o c e s s o r e n d i a n m o d e s . W h e n t h e I M U t e s t a n d s e t r e g i s t e r a r r a y
F i g u r e 1 2 0
F i g u r e 1 2 1 .
®
P r o c e s s o r r u n n i n g i n B i g E n d i a n M o d e
+3
+2
Byte Address 3 Byte Address 2
Byte Address 0 Byte Address 1
D[31:24]
D[23:16]
+0
+1
®
P r o c e s s o r r u n n i n g i n L i t t l e E n d i a n M o d e
+3
+2
Byte Address 2
Byte Address 2
D[31:24]
D[23:16]
+3
+2
®
p r o c e s s o r d r i v e s b y t e f o r a d d r e s s 0
®
p r o c e s s o r d r i v e s b y t e f o r a d d r e s s 0 o n
®
p r o c e s s o r , t h e I M U d e t e c t s t h e e n d i a n m o d e
®
p r o c e s s o r i s r u n n i n g i n b i g e n d i a n
. O t h e r w i s e , i f t h e I n t e l X S c a l e
+1 +0
Byte Address 1 Byte Address 0
Byte Adress 2 Byte Address 3
D[15:08] D[07:00]
+2 +3
+1 +0
Byte Address 1 Byte Address 0
Byte Address 1 Byte Address 0
D[15:08] D[07:00]
+1 +0
I n t e l
®
p r o c e s s o r i s
IMU Byte Address
Aligned 32-Bit Word in
Test and Set Register
Array (Little Endian
Order)
An aligned 32-Bit Word
on Internal Data Bus in
Big Endian Mode
32-bit portion of the
Internal Data Bus
Byte Address in Big
Endian Mode
IMU Byte Address
Aligned 32-Bit Word in
Test and Set Register
Array (Little Endian
Order)
An aligned 32-Bit Word
on Internal Data Bus in
Little Endian Mode
32-bit portion of the
Internal Data Bus
Byte Address in Little
Endian Mode
®
8 1 3 4 1 a n d 8 1 3 4 2 I / O P r o c e s s o r s
D e v e l o p e r ' s M a n u a l
®
8 5 9