Intel 81342 Developer's Manual page 964

1 8 . 5 . 4 P M O N F e a t u r e E n a b l e R e g i s t e r - P M O N E N
C o n t a i n s c o n t r o l b i t s f o r
T a b l e 6 0 5 . P M O N F e a t u r e E n a b l e R e g i s t e r - P M O N E N
31
IOP
rv rv rv
Attributes
PCI
rv rv rv
Attributes
I n t e r n a l B u s A d d r e s s O f f s e t
+ 0 4 0 h
B i t D e f a u l t
3 1 : 2 0 0 0 0 0 0 0 0 h R e s e r v e d
P M O N I n d i c a t o r O u t p u t E n a b l e .
g e n e r a t e a s i g n a l o n t h e
d o c u m e n t e d e l s e w h e r e i n t h i s d o c u m e n t , t h i s b i t s i m p l y p r o v i d e s a g l o b a l m a s k .
0 = D o N O T g e n e r a t e
1 0 b
1 = D O g e n e r a t e
N o t e :
0 0 b I n t e r r u p t E n a b l e : E n a b l e s 8 1 3 4 1 a n d 8 1 3 4 2
1 8 . 5 . 5 P M O N S t a t u s R e g i s t e r - P M O N S T A T
C o n t a i n s s t a t u s b i t s f o r
T a b l e 6 0 6 . P M O N S t a t u s R e g i s t e r - P M O N S T A T
31
IOP
rv rv rv
Attributes
PCI
rv rv rv
Attributes
I n t e r n a l B u s A d d r e s s O f f s e t
+ 0 4 4 h
B i t D e f a u l t
3 1 : 1 0 0 0 0 0 0 0 0 h R e s e r v e d
I n t e r r u p t S t a t u s : I n d i c a t e s a p e n d i n g i n t e r r u p t f r o m
I n t e r r u p t E n a b l e b i t i n t h e
0 0 b
0 =
1 =
®
I n t e l 8 1 3 4 1 a n d 8 1 3 4 2 I / O P r o c e s s o r s
D e v e l o p e r ' s M a n u a l
9 6 4
P M O N
u n i t .
28 24 20
rv rv rv rv rv rv rv rv rv rv
rv rv rv rv rv rv rv rv rv rv
G P I O [ 7 ]
P M O N I n d i c a t o r O u t p u t ( d e f a u l t ) .
P M O N
I n d i c a t o r O u t p u t w h i c h g o e s t o t h e o p t i o n a l o u t p u t p i n (
P M O N
T h e I n d i c a t o r O u t p u t E n a b l e o v e r r i d e s t h e
Output Enable Register — GPOE" on page 943
P M O N u n i t .
28 24 20
rv rv rv rv rv rv rv rv rv rv
rv rv rv rv rv rv rv rv rv rv
P M O N
P M O N
I n t e r r u p t i s N O T p e n d i n g
P M O N
I n t e r r u p t I S p e n d i n g
I n t e l
16 12
rv rv rv rv rv rv rv rv rv
rv rv rv rv rv rv rv rv rv
A t t r i b u t e L e g e n d :
R V = R e s e r v e d
P R = P r e s e r v e d
R S = R e a d / S e t
D e s c r i p t i o n
P M O N
S p e c i f i e s t h a t t h e u n i t i n d i c a t o r s h o u l d b e a l l o w e d t o
o u t p u t p i n . T h e c o n d i t i o n s t h a t c a n c a u s e t h i s s i g n a l t o b e t o g g l e a r e
G P I O [ 7 ]
P M O N
u n i t g e n e r a t e d i n t e r r u p t s .
16 12
rv rv rv rv rv rv rv rv rv
rv rv rv rv rv rv rv rv rv
A t t r i b u t e L e g e n d :
R V = R e s e r v e d
P R = P r e s e r v e d
R S = R e a d / S e t
D e s c r i p t i o n
P M O N
u n i t . T h i s b i t c a n o n l y b e s e t w h e n t h e
E N r e g i s t e r i s s e t .
®
8 1 3 4 1 a n d 8 1 3 4 2 — P M O N U n i t
8 4
rv rv rv rv rv rv rv rv rw rw
rv rv rv rv rv rv rv rv rw rw
R W = R e a d / W r i t e
R C = R e a d C l e a r
R O = R e a d O n l y
N A = N o t A c c e s s i b l e
G P I O [ 7 ]
) .
Section 17.2.1, "GPIO
s e t t i n g i n
8 4
rv rv rv rv rv rv rv rv rv rc
rv rv rv rv rv rv rv rv rv rc
R W = R e a d / W r i t e
R C = R e a d C l e a r
R O = R e a d O n l y
N A = N o t A c c e s s i b l e
D e c e m b e r 2 0 0 7
O r d e r N u m b e r : 3 1 5 0 3 7 - 0 0 2 U S
0
0