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1 5 . 4 . 6
U A R T x L i n e C o n t r o l R e g i s t e r
I n t h e L i n e C o n t r o l R e g i s t e r , t h e s y s t e m p r o g r a m m e r s p e c i f i e s t h e f o r m a t o f t h e
a s y n c h r o n o u s d a t a c o m m u n i c a t i o n s e x c h a n g e . T h e s e r i a l d a t a f o r m a t c o n s i s t s o f a s t a r t
b i t ( l o g i c 0 ) , f i v e t o e i g h t d a t a b i t s , a n o p t i o n a l p a r i t y b i t , a n d o n e o r t w o s t o p b i t s
( l o g i c 1 ) . T h e L C R h a s b i t s f o r a c c e s s i n g t h e D i v i s o r L a t c h r e g i s t e r s a n d c a u s i n g a B r e a k
c o n d i t i o n . T h e p r o g r a m m e r c a n a l s o r e a d t h e c o n t e n t s o f t h e L i n e C o n t r o l R e g i s t e r . T h e
r e a d c a p a b i l i t y s i m p l i f i e s s y s t e m p r o g r a m m i n g a n d e l i m i n a t e s t h e n e e d f o r s e p a r a t e
s t o r a g e i n s y s t e m m e m o r y .
T a b l e 5 7 0 . U A R T x L i n e C o n t r o l R e g i s t e r - ( U x L C R ) ( S h e e t 1 o f 2 )
e s
3 1
u t
P
i b
r v
I O
t r
A t
e s
u t
I
P C
i b
n a
t r
A t
U n i t #
0
1
B i t
31:8
7
6
5
®
I n t e l
8 1 3 4 1 a n d 8 1 3 4 2 I / O P r o c e s s o r s
D e v e l o p e r ' s M a n u a l
8 9 6
2 8
2 4
r v
r v
r v
r v
r v
r v
r v
r v
r v
r v
r v
n a
n a
n a
n a
n a
n a
n a
n a
n a
n a
n a
®
I n t e l X S c a l e
C o r e i n t e r n a l b u s a d d r e s s
+ 2 3 0 C H ( D L A B = x )
+ 2 3 4 C H ( D L A B = x )
D e f a u l t
00 0000h
Reserved
Divisor Latch register Access Bit (DLAB): This bit must be set (1) to access the
Divisor Latches of the Baud Rate Generator during a READ or WRITE operation. It
must be clear (0) to access the Receiver Buffer, the Transmit-Holding Register, or
the Interrupt-Enable Register. This bit does not have to be set when using autobaud.
0
2
0 = access Transmit Holding register (THR), Receive Buffer Register (RBR) and
Interrupt Enable Register.
1 = access Divisor Latch Registers (DLL and DLH).
Set break (SB): Causes a Break condition to the receiving UART. When SB is set
(1), the serial output (TXD) is forced to the spacing (logic 0) state and remains there
until SB is clear (0). This bit acts only on the TXD pin and has no effect on the
transmitter logic.
0
2
In FIFO mode, wait for the transmitter to be idle (TEMT=1) to set and clear the break
bit.
0 = no effect on TXD output.
1 = forces TXD output to 0 (space).
Sticky Parity (STKYP): Can be used in multiprocessor communications. When PEN
and STKYP are set (1), the bit that is transmitted in the parity bit location (the bit just
before the stop bit) is the complement of the EPS bit. When EPS is 0, then the bit at
the parity bit location is transmitted as a 1. In the receiver, when STKYP and PEN
are 1, then the receiver compares the bit that is received in the parity bit location with
the complement of the EPS bit. When the values being compared are not equal, the
receiver sets the Parity Error bit in LSR and causes an error interrupt when line
status interrupts were enabled. For example, when EPS is 0, the receiver expects
0
2
the bit received at the parity bit location to be 1. When it is not, then the parity error
bit is set. By forcing the bit value at the parity bit location, rather than calculating a
parity value, a system with a master transmitter and multiple receivers can identify
some transmitted characters as receiver addresses and the rest of the characters as
data. When PEN = 0, STKYP is ignored.
0 = no effect on parity bit.
1 = Forces parity bit to be opposite of EPS bit value.
2 0
1 6
1 2
r v
r v
r v
r v
r v
r v
r v
r v
r v
r v
n a
n a
n a
n a
n a
n a
n a
n a
n a
n a
A t t r i b u t e L e g e n d :
R V = R e s e r v e d
P R = P r e s e r v e d
R S = R e a d / S e t
D e s c r i p t i o n
®
I n t e l
8 1 3 4 1 a n d 8 1 3 4 2 — U A R T s
8
4
0
r v
r v
r w
r w
r w
r w
r w
r w
r w
r w
n a
n a
n a
n a
n a
n a
n a
n a
n a
n a
R W = R e a d / W r i t e
R C = R e a d C l e a r
R O = R e a d O n l y
N A = N o t A c c e s s i b l e
D e c e m b e r 2 0 0 7
O r d e r N u m b e r : 3 1 5 0 3 7 - 0 0 2 U S
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