Intel 81342 Developer's Manual page 894

1 5 . 4 . 5 U A R T x F I F O C o n t r o l R e g i s t e r
F C R i s a w r i t e o n l y r e g i s t e r t h a t i s l o c a t e d a t t h e s a m e a d d r e s s a s t h e I I R ( I I R i s a r e a d
o n l y r e g i s t e r ) . F C R e n a b l e s / d i s a b l e s t h e t r a n s m i t t e r / r e c e i v e r F I F O s , c l e a r s t h e
t r a n s m i t t e r / r e c e i v e r F I F O s , a n d s e t s t h e r e c e i v e r F I F O t r i g g e r l e v e l .
T a b l e 5 6 9 . U A R T x F I F O C o n t r o l R e g i s t e r - ( U x F C R ) ( S h e e t 1 o f 2 )
s
3 1
t e
P
b u
r v
I O r i
t t
A
s
t e
I
b u
P C n a
r i
t t
A
U n i t #
0
1
B i t
31:8
7:6
5:4
3
®
I n t e l 8 1 3 4 1 a n d 8 1 3 4 2 I / O P r o c e s s o r s
D e v e l o p e r ' s M a n u a l
8 9 4
2 8 2 4
r v r v r v r v r v r v r v r v r v r v
n a n a n a n a n a n a n a n a n a n a
®
I n t e l X S c a l e C o r e i n t e r n a l b u s a d d r e s s
+ 2 3 0 8 H ( D L A B = x )
+ 2 3 4 8 H ( D L A B = x )
D e f a u l t
00 0000h Reserved
Interrupt Trigger Level (ITL): When the number of bytes in the receiver FIFO
equals the interrupt trigger level programmed into this field and the Received Data
Available Interrupt is enabled (via IER), an interrupt is generated and appropriate
bits are set in the IIR.
00
00 = 1 byte or more in FIFO causes interrupt
2
01 = 8 bytes or more in FIFO causes interrupt
10 = 16 bytes or more in FIFO causes interrupt
11 = 32 bytes or more in FIFO causes interrupt
0 Preserved
2
Transmitter Interrupt Level (TIL): Setting TIL causes Transmitter Interrupts to
occur when the Transmit FIFO is empty. Clearing TIL causes Transmitter Interrupts
to occur when the Transmit FIFO is half empty.
0
2
0 = Interrupt when FIFO is half empty
1 = Interrupt when FIFO is empty
2 0 1 6 1 2
r v r v r v r v r v r v r v r v r v r v
n a n a n a n a n a n a n a n a n a n a
A t t r i b u t e L e g e n d :
R V = R e s e r v e d
P R = P r e s e r v e d
R S = R e a d / S e t
D e s c r i p t i o n
®
I n t e l 8 1 3 4 1 a n d 8 1 3 4 2 — U A R T s
8 4
r v r v r v w o w o p r p r w o w o w o
n a n a n a n a n a n a n a n a n a n a
R W = R e a d / W r i t e
R C = R e a d C l e a r
R O = R e a d O n l y
N A = N o t A c c e s s i b l e
D e c e m b e r 2 0 0 7
O r d e r N u m b e r : 3 1 5 0 3 7 - 0 0 2 U S
0
w o
n a