Table E-1 P1 Vme Pin Assignments - Silicon Graphics POWER CHALLENGE User Manual

Appendix E: Challenge VMEbus Implementation
VME Pins
136
Note that in some VME enclosures, these plates supply the required
additional EMI shielding. However, the Challenge chassis already provides
sufficient shielding for boards inside the chassis, so these plates are not
necessary.
Table E-1 through Table E-3 list the pin assignments of the VME P1, P2, and
P3 connectors. Table E-4 describes the pin signals.
No connections are made to rows A and C of connector P2. These lines
Note:
are not bused across the backplane. The P3 connector uses the SUN power
convention. In addition, the Challenge system does not generate ACFAIL* or
SYSFAIL*. The SERCLK and SERDAT* are also unused.
The Challenge system supplies the defined voltages to the bus and also
asserts SYSREST* and drives SYSCLK (SYSCLK is driven at 16 MHz).
On Challenge system backplanes, the unused VME pins on P1/P2/P3 are no
connects.
Table E-1 P1 VME Pin Assignments
Pin Row A
1 D00
2 D01
3 D02
4 D03
5 D04
6 D05
7 D06
8 D07
9 GND
10 SYSCLK
Row B Row C
BBSY* D08
BCLR* D09
ACFAIL D10
BG01N* D11
BG0OUT* D12
BG1IN* D13
BG1OUT* D14
BG2IN* D15
BG2OUT* GND
BG3IN* SYSFAIL*