Silicon Graphics POWER CHALLENGE User Manual page 157

Table E-4 (continued)
Signal Name Definition
DTACK Data transfer acknowledge. Asserted by SLAVE to indicate a
successful bus transfer.
WRITE Write not or read.
LWORD Indicates long word transfer (D32).
SYSCLK 16 MHz system clock. (Does not control bus timing.)
SERCLK Serial data clock.
SERDAT Serial data line.
BERR Bus error line.
SYSFAIL Indicates a board has failed.
ACFAIL AC power failure notify line.
SYSRESET Reset signal for VME bus.
Signal Definitions
VME Pins
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