Silicon Graphics POWER CHALLENGE User Manual page 156

Appendix E: Challenge VMEbus Implementation
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Table E-4 Signal Definitions
Signal Name Definition
D00 through Data lines. These lines are tri-state and are not defined until the
D31 data strobes (DS0* and DS1*) are asserted by the MASTER.
A00 through Address lines. These lines are tri-state and are not defined until
A31 the address strobe (AS*) is asserted by the MASTER.
AM0 through Address modifier lines. Asserted by the MASTER and indicates
AM5 the type of data transfer to take place. VME SLAVEs look at the
lines to determine if they will respond and what type of response
to make.
DS0, DS1 Data Strobe lines. Asserted by the MASTER and indicates stable
data on the data bus.
AS Address strobe. Is asserted by the MASTER and indicates a stable
address is present on the address lines.
BR0 through Bus request lines. The MASTER requests a busy bus via these
BR3 prioritized levels.
BG0IN through Bus grant in (daisy-chained).
BG3IN
BG0OUT Bus grant out (daisy-chained).
through
BG3OUT
BBSY Busy.
BCLR Bus clear. (Hint to bus master, VME MASTERs are not required
to comply.)
IRQ1 - IRQ7 Interrupt request lines.
IACK Interrupt acknowledge. Asserted by MASTER to indicate the
VME interrupt level to be serviced.
IACKIN Interrupt acknowledge in (daisy-chained).
IACKOUT Interrupt acknowledge in (daisy-chained).