Memory Map; Cpld Register Definitions; Table 3-1. Board Address Space Usage; Table 3-2. Register0 - IBM PPC750FX User Manual

Preliminary

3. Memory Map

Table 3-1 provides a summary of the board address space usage. For details about address space usage
relating to the processor registers, refer to the PPC750FX Embedded Processor User's Manual.

Table 3-1. Board Address Space Usage

Peripheral
DDR SDRAM
MV64360 Integrated SRAM
FRAM
ST16C2552 UART Channel B
ST16C2552 UART Channel A
CPLD Registers
MV64360 Registers
32-bit Flash
SRAM
8-bit Flash
Note: The base addresses of peripherals attached to the MV64360 system controller device are software dependent. The values in the
table above are used by the PPC750FX Evaluation Kit Software. Other software environments may use different values for the
peripheral base addresses.

3.1 CPLD Register Definitions

This section provides description by bit for each of the CPLD registers.
Each CPLD register is 8 bits wide. In the tables below, the most significant bit is bit 0, and the least significant
bit is bit 7. The CPLD source code uses the reverse bit ordering.

Table 3-2. Register0

Bit Name
0:7 CPLD Revision
750FXebm_ch3.fm
June 10, 2003
Start Address End Address
0x00000000 0x0FFFFFFF
0x42000000 0x4203FFFF
0xEF500000 0xEF507FFF
0xEF600000 0xEF600007
0xEF600008 0xEF60000F
0xEF700000 0xEF700004
0xF1000000 0xF100FFFF
0xFC000000 0xFDFFFFFF
0xFFE00000 0xFFEFFFFF
0xFFF00000 0xFFFFFFFF
R/W
R Revision level of CPLD code
Evaluation Board Manual
PPC750FX Evaluation Board
Chip Select
SDRAM CS0 and CS1
n/a
DevCS3
DevCS2
DevCS2
DevCS1
n/a
DevCS0
BootCS
BootCS
Description
Page 27 of 115
Size
256MB
256KB
32KB
8B
8B
5B
64KB
32MB
1MB
1MB
Memory Map