Timing-Registers And Control Functions; Maximum Clock Frequency; Clock-To-Output Time; Table 11-4. Maximum Clock Frequency - IBM PPC750FX User Manual

Evaluation Board Manual
PPC750FX Evaluation Board
11.2 Timing—Registers and Control Functions
The timing data in the following tables are based on simulation.

11.2.1 Maximum Clock Frequency

Table 11-4 provides the actual frequency at which the indicated clock is running, and the highest frequency at
which it can be allowed to run before the period becomes shorter than the worst case signal propagation time.

Table 11-4. Maximum Clock Frequency

Clock
pld25mhz
dev_we_n[0]
pld_sysclk

11.2.2 Clock-to-Output Time

Table 11-5 provides the longest and shortest input-to-output delay for each output signal clocked through a
register for the all clocks that gate the signal.

Table 11-5. Clock-to-Output Time

Output Signal
big_flash_cs_n
cpu_mcp0
cpu_mcp1
cpu_tben
cpu_trst_n
cpu0_hreset_n
cpu0_hreset_n
cpu0_smi_n
cpu0_sreset_n
cpu0_sreset_n
cpu1_hreset_n
cpu1_hreset_n
cpu1_smi_n
cpu1_sreset_n
cpu1_sreset_n
dev_adr[0]
dev_adr[0]
dev_adr[1]
dev_adr[1]
dev_adr[2]
CPLD Programming
Page 94 of 115
Actual Operating Frequency
25MHz
None
133.33MHz
Clock
ale
dev_we_n[0]
dev_we_n[0]
dev_we_n[0]
pld25mhz
dev_we_n[0]
pld25mhz
dev_we_n[0]
dev_we_n[0]
pld25mhz
dev_we_n[0]
pld25mhz
dev_we_n[0]
dev_we_n[0]
pld25mhz
ale
dev_we_n[0]
ale
dev_we_n[0]
ale
Allowed Maximum Frequency (period)
166.67MHz (6ns)
181.82MHz (5.5ns)
185.19MHz (5.4ns)
Longest Delay (ns)
9.100
10.900
10.900
10.900
26.400
15.500
23.100
10.900
14.700
14.500
19.200
26.800
10.900
14.700
14.500
12.500
9.500
12.500
9.400
12.500
Preliminary
Shortest Delay (ns)
9.100
10.900
10.900
10.900
18.500
15.500
15.200
10.900
14.700
14.400
19.200
18.900
10.900
14.700
14.400
12.500
9.400
12.500
9.400
12.500
750FXebm_ch11.fm
June 10, 2003