Table 6-7. System Controller Initilization-U24 - IBM PPC750FX User Manual

Preliminary
Table 6-7. System Controller Initilization—U24
Switch No. Signal
1 DEV_AD19
2 DEV_AD21
3 DEV_AD22
4 DEV_AD23
5 DEV_AD24
PCIMODE_TARGET/
6
HOST_N
7 FLASH_N/SRAM_SEL
8 DEV_AD14
750FXebm_ch6.fm
June 10, 2003
Default Setting
ON = DDR SDRAM address/control signals toggle on falling edge of
DRAM clock.
OFF
OFF = DDR SDRAM address/control signals toggle on rising edge of
DRAM clock.
ON = DDR SDRAM two pipe stages (up to 133MHz SDRAM clock)
ON
OFF = DDR SDRAM three pipe stages (up to 183MHz SDRAM clock)
ON = DDR SDRAM read data is synchronized to the MV64360 core clock.
ON OFF = DDR SDRAM read data is synchronized to the MV64360 FBClkIn
clock signal.
DDR SDRAM Read Control Logic Delay
ON
ON = Disabled
OFF = Enabled
DDR SDRAM Read Data Delay
ON
ON = Disabled
OFF = Enabled
ON = board operates as a PCI Host
OFF
OFF = board operates as a PCI Adapter
ON = 8-bit Flash resides at a higher address than the 8-bit SRAM
OFF = 8-bit SRAM resides at a higher address than the 8-bit Flash
ON
Note: This switch can be useful for putting SRAM at the CPU reset vector
during boot ROM code development.
This switch should always be in the ON position since only 8- or 32-bit
ON
wide devices are available for booting.
PPC750FX Evaluation Board
Description (0 = ON = closed, 1 = OFF = open)
Evaluation Board Manual
Switches
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