Figure 1-1. Ppc750Fx Block Diagram - IBM PPC750FX User Manual

Evaluation Board Manual
PPC750FX Evaluation Board

Figure 1-1. PPC750FX Block Diagram

Completion
System
Unit
FXU2
FXU1
32KB D-Cache
with parity
The PPC750FX processor has the following features:
• Branch processing unit
- Four instructions fetched per clock.
- One branch processed per cycle (plus resolving two speculations).
- Up to one speculative stream in execution, one additional speculative stream in fetch.
- 512-entry branch history table (BHT) for dynamic prediction.
- 64-entry, 4-way set associative branch target instruction cache (BTIC) for eliminating branch delay
slots.
• Dispatch unit
- Full hardware detection of dependencies (resolved in the execution units).
- Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1
(FXU1), fixed-point unit 2 (FXU2), or floating-point).
- Four-stage pipeline: fetch, dispatch, execute, and complete.
- Serialization control (predispatch, postdispatch, execution, serialization).
Overview
Page 14 of 115
Control Unit
Instruction Fetch
Branch Unit
Dispatch
GPRs
LSU
Rename
Buffers
L2 Tags
32KB I-Cache
BHT/BTIC
FPRs
Rename
Buffers
512KB
L2 Cache
with ECC
Preliminary
with parity
FPU
Enhanced
60X
BIU
750FXebm_ch1.fm
June 10, 2003