IBM PPC750FX User Manual page 75

Preliminary
Table 11-2. CPLD I/O Pin List (Continued)
Name
cpu0_hreset_n
cpu_trst_n
cpu1_sreset_n
cpu1_hreset_n
cpu0_sreset_n
lcs_n[1]
mpp_reset_out_n
GND
~VREFB~
atx_ok_n
~TCK~
dev_we_n[0]
lcs_n[0]
bootsmall_n
VCCIO2
badr[2]
rw_sreset
jtag_chkstop_n
cpu_tben
cpu1_smi_n
cpu0_smi_n
~TDO~
GND
lcs_n[3]
mpp0_hreset_n
ldev_addr[21]
cstiming_n
unused_pin
cpu_mcp1
cpu_mcp0
VCCIO2
mpp1_sreset_n
rw_hreset
switch_b
GND
pld_sysclk
target/host_n
750FXebm_ch11.fm
June 10, 2003
Pin
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Evaluation Board Manual
PPC750FX Evaluation Board
Function
Output
Output
Output
Output
Output
Input
Input
Gnd
Input
Input
Input
Input
Input
Input
Power
Input
Input
Output
Output
Output
Output
Output
Gnd
Input
Input
Input
Input
Output
Output
Output
Power
Input
Input
Input
Gnd
Input
Input
CPLD Programming
Page 75 of 115