Misc Logic - IBM PPC750FX User Manual

Preliminary

11.1.2.7 misc Logic

The following logic diagram defines the function of the logic in the misc part of the CPLD:
pld25mhz
pld25mhz INPUT
VCC
mpp_reset_out_n
mpp_reset_out_n INPUT
VCC
mpp_block_n
mpp_block_n INPUT
VCC
pwrgd
pwrgd INPUT
VCC
INPUT
dev_adr0
VCC
sysreset_n INPUT
VCC
cpu0_chkstop_n INPUT
VCC
cpu1_chkstop_n INPUT
VCC
750FXebm_ch11.fm
June 10, 2003
LPM_COUNTER
cnt_en
q[]
7
OR2
LCELL NOT
NOT
13 8
inst2 inst6
LPM_CONSTANT
result[]
(cvalue)
10
pld25mhz
DFF DFF
LCELL
PRN
D Q
108
CLRN
4 5
dev_adr0
LCELL
sysreset_n
14
cpu0_chkstop_n AND2
cpu1_chkstop_n
355
LPM_COMPARE
aeb
dataa[]
datab[]
aneb
9
DFF
PRN
D Q
pld25mhz
CLRN
11
a little filtering because of slow risetime
PRN
D Q
AND3 DFF
D
12
CLRN
6
DFF
serial_eeprom
PRN
D Q
CLRN
16
jtag_chkstop_n
Evaluation Board Manual
PPC750FX Evaluation Board
mpp_reset_2ms_n
OUTPUT mpp_reset_2ms_n
del_powergood
PRN
OUTPUT del_powergood
Q
CLRN
OUTPUT
serial_eeprom
OUTPUT jtag_chkstop_n
CPLD Programming
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