IBM PPC750FX User Manual page 16

Evaluation Board Manual
PPC750FX Evaluation Board
- Pseudo-LRU replacement.
- Copy-back or write-through data cache (on a page per page basis).
- Parity on L1 tags and arrays.
- Three-state (MEI) memory coherency.
- Hardware support for data coherency.
- Non-blocking instruction cache (one outstanding miss).
- Non-blocking data cache (two outstanding misses).
- No snooping of instruction cache.
• Memory management unit
- 64-entry, 2-way set associative instruction TLB (total 128).
- 64-entry, 2-way set associative data TLB (total 128).
- Hardware reload for TLB's.
- Eight instruction BAT's and eight data BATs.
- Virtual memory support for up to 4PB (2
- Real memory support for up to 4GB (2
- Support for big/little-endian addressing.
• Dual PLLs
- Allows seamless frequency switching.
• Level 2 (L2) cache
- Internal L2 cache controller and 4K-entry tags; 512KB data SRAMs.
- Two-way set associative, supports locking by way.
- Copy-back or write-through data cache on a page basis, or for all L2.
- 64-byte sectored line size.
- L2 frequency at core speed.
- ECC protection on SRAM array.
- Parity on L2 tags.
- Supports up to 2 outstanding misses (1 data and 1 instruction or 2 data).
• Bus interface
- 32-bit address bus.
- 64-bit data bus (can be operated in 32-bit mode).
- Core-to-bus frequency multipliers of 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 8.5x, 9x, 9.5x, 10x,
11x, 12x, 13x, 14x, 15x, 16x, 17x, 18x, 19x, and 20x supported.
- Supports 1.8V, 2.5V, or 3.3V I/O modes.
• Power
- Low power consumption with low voltage.
- Dynamic power management.
- Three static power saving modes: doze, nap, and sleep.
- Thermal Assist Unit (TAU).
Overview
Page 16 of 115
52
) virtual memory.
32
) of physical memory.
Preliminary
750FXebm_ch1.fm
June 10, 2003