Top Level Block Diagram 1 - IBM PPC750FX User Manual

Preliminary

11.1.2.1 Top Level Block Diagram 1

badr0
badr1
badr2
pld_sysclk
sysreset_n
lcs_n3
cstiming_n
sysreset_n
PLD_SYSCLK
cstiming_n
lboot_cs_n
lcs_n[3..0]
ldev_addr[21..19]
flash_n/sram_sel
bootsmall_n
ldevr_w_n
dev_we_n[0]
nvram_burst_cs_n
sysreset_n
cstiming_n
dev_we_n[0]
ale
fpga_cs_n
badr[2..0]
target/host_n
flash_n/sram_sel
bootsmall_n
switch_a
switch_b
atx_ok_n
750FXebm_ch11.fm
June 10, 2003
framcs
badr0 nvram_burst_cs_n
badr1
badr2
sysclock
sysreset
lcs_n[3]
cstiming_n
inst4
decode_block
sysreset_n small_flash_lo_cs_n
sysclk small_flash_hi_cs_n
CSTiming_n
LBootCS_n
lcs_n[3..0]
ldev_addr[21..19]
flash_n/sram_sel
bootsmall_n
ldevR_W_n
Dev_We_n0
nvram_burst_cs_n
inst7
registers2
sysreset_n dev_ad[7..0]
cstiming_n ldevR_W_n
we_n0 lboot_cs_n
ale
fpga_cs_n
badr[2..0]
target/host_n cpu0_smi_n
flash_n/sram_sel cpu1_smi_n
bootsmall_n cpu_tben
switch_a cpu_mcp0
switch_b cpu_mcp1
ATX_OK_N
mpp_block_n
inst
nvram_burst_cs_n
small_flash_cs_n
small_flash_hi_cs_n
sram_cs_n
sram_lo_cs_n
sram_hi_cs_n
sram_hi_cs_n
big_flash_cs_n
big_flash_cs_n
read_n
Read_n
write_n
Write_n
uart_cs_n
uart_cs_n
nvram_cs_n
nvram_cs_n
testpin_d
test
fpga_cs_n
fpga_cs_n
dev_adr[7..0]
ldevr_w_n
lboot_cs_n
led0
led0
led1
led1
led2
led2
cpu0_smi_n
cpu1_smi_n
cpu_tben
cpu_mcp0
cpu_mcp1
read_oe
mpp_block_n
Evaluation Board Manual
PPC750FX Evaluation Board
CPLD Programming
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