Cpld Logic; Table 11-3. Cpld Logic Descriptions - IBM PPC750FX User Manual

Evaluation Board Manual
PPC750FX Evaluation Board
Table 11-2. CPLD I/O Pin List (Continued)
Name
GND+
pld25mhz
VCCINT
dev_adr[0]
dev_adr[1]
dev_adr[2]
GND
dev_adr[3]
dev_adr[4]
ldev_addr[20]
cpufan_ok_n
ldev_addr[19]

11.1.2 CPLD Logic

The folllowing sections provided a representation of the logic of the complete CPLD in either graphical or
code listing format.

Table 11-3. CPLD Logic Descriptions

Section
Top Level Block Diagram 1
Top Level Block Diagram 2
framcs Logic
decode_block Program
registers2 Program
reset_block Program
misc Logic
CPLD Programming
Page 76 of 115
Pin
89
90
91
92
93
94
95
96
97
98
99
100
Description
First three of five CPLD logic sections
Last two of five CPLD logic sections
framcs detailed logic diagram
decode_block code listing
register2 code listing
reset_block code listing
misc detailed logic diagram
Preliminary
Function
Input
Power
Bidir
Bidir
Bidir
Gnd
Bidir
Bidir
Input
Input
Input
Page
77
78
79
80
84
89
93
750FXebm_ch11.fm
June 10, 2003