Internal Processor Clocking; System Controller; Sdram Interface; Pci Bus - IBM PPC750FX User Manual

Preliminary

2.3 Internal Processor Clocking

The PPC750FX requires a single system clock input SYSCLK. The frequency of this input determines the
frequency of the PPC750FX bus interface. Internally, the PPC750FX uses a phase-lock loop (PLL) circuit to
generate a master core clock that is frequency-multiplied and phase-locked to the SYSCLK input. The PLL in
the PPC750FX is configured using seven pins PLL_CFG(0:4) and PLL_RANGE(0:1). On the PPC750FX
evaluation board, the configuration of these pins is controlled by switch settings (see Section 6 Switches on
page 39).

2.4 System Controller

The board contains a Marvell MV64360 system controller that connects to the 60x bus of the PPC750FX, and
provides an interface to DDR SDRAM, the PCI bus, the integrated Ethernet MACs, the integrated SRAM, an
interrupt controller, DMA engines, and an interface to attach external devices. Hereafter, in this document,
this component is referred to as the system controller.

2.5 SDRAM Interface

This board provides 256MB of permanently mounted DDR SDRAM operating at 133.33MHz. The interface to
the SDRAM is through the system controller, and is accessed using DRAM chip selects CS0 and CS1. The
SDRAM on the board is 72 bits wide and allows the use of the SDRAM Error Checking and Correction (ECC)
feature in the system controller if desired.

2.6 PCI Bus

This PPC750FX evaluation board is a full-length PCI card and is intended to be operated while plugged into a
PCI slot in a personal computer or a PCI backplane. However, because an ATX power connector is provided,
it can be operated without being plugged into a PCI slot. If this external mode of operation is used, the PCI
bus will not be available.

2.7 Ethernet

The board provides two 100BASE-TX Ethernet interfaces. The physical layer for both Ethernet ports is
provided by the BCM5222 which contains two medium-independent interface (MII) PHYs. The five address
pins of the BCM5222 are tied to ground making the addresses of the two PHYs 0 and 1. Table 2-1 shows the
relationship between the two Ethernet ports being used in the MV64360, the PHY to which each port is
connected in the BCM5222, the address of each PHY, and finally the RJ45 connectors for each port (see J20
in Figure 10-1 on page 54).

Table 2-1. Ethernet Ports

MV64360 Ethernet Port No.
0
1
750FXebm_ch2.fm
June 10, 2003
Serial Manangement Interface
BCM522 PHY No.
2
1
Evaluation Board Manual
PPC750FX Evaluation Board
PHY Address
1
0
RJ45 Connector
1
2
Board Design
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