IBM PPC750FX User Manual page 99

Preliminary
Table 11-6. Pin-to-Pin Signal Delay (Continued)
Source
ldev_addr[20]
ldev_addr[20]
ldev_addr[20]
mpp0_hreset_n
mpp0_sreset_n
mpp1_hreset_n
mpp1_sreset_n
pci_reset_n
pci_reset_n
pci_reset_n
pci_reset_n
pci_reset_n
pci_reset_n
target/host_n
target/host_n
target/host_n
target/host_n
target/host_n
target/host_n
target/host_n
750FXebm_ch11.fm
June 10, 2003
Destination
sram_cs_n
sram_hi_cs_n
textpin_d
cpu0_hreset_n
cpu0_sreset_n
cpu1_hreset_n
cpu1_sreset_n
cpu_trst_n
cpu0_hreset_n
cpu1_hreset_n
led_red_n
sysreset
sysreset_n
cpu_trst_n
cpu0_hreset_n
cpu1_hreset_n
led_red_n
pci_reset_n
sysreset
sysreset_n
Evaluation Board Manual
PPC750FX Evaluation Board
Longest Delay (ns) Shortest Delay (ns)
5.200
5.200
5.400
10.600
10.200
14.700
10.200
14.500
11.200
14.900
5.200
10.200
10.200
14.200
10.900
14.600
5.300
4.300
10.300
10.300
5.200
5.200
5.400
10.200
10.200
13.900
10.200
14.100
10.400
14.500
5.200
10.200
10.200
14.200
10.500
14.200
5.300
4.300
10.300
10.300
CPLD Programming
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