Evaluation Board Manual
PPC750FX Evaluation Board
PCI Connector Signals-J25 ..................................................................................................59
CPLD JTAG Connector-J26 .................................................................................................62
Table 10-13. Test Connections ....................................................................................................................69
Section Contents ....................................................................................................................73
CPLD I/O Pin List ...................................................................................................................73
CPLD Logic Descriptions ........................................................................................................76
Maximum Clock Frequency ....................................................................................................94
Clock-to-Output Time .............................................................................................................94
Pin-to-Pin Signal Delay ...........................................................................................................96
Setup and Hold Time ............................................................................................................100
Section Contents ..................................................................................................................101
Debugging Tools ..................................................................................................................104
Auxiliary Materials in Kit .......................................................................................................104
Tables
Page 8 of 115
Preliminary
750FXebmLOT.fm
June 10, 2003