Table 3-3. Register1; Table 3-4. Register2 - IBM PPC750FX User Manual

Evaluation Board Manual
PPC750FX Evaluation Board

Table 3-3. Register1

Note: This register should be written before reading in order to latch the most current status. Any value can be written to the register.
Bit Name
0 (msb) na
1 na
2 ATX or PCI Power
3 Spare Switch B
4 Spare Switch A
5 PCI Adapter/Host select
6 8-bit Flash/SRAM swap select
7 (lsb) BootFlash select

Table 3-4. Register2

Bit Name
0 (msb) CPU1 MCP control
1 CPU0 MCP control
2 CPU TBEN control
3 CPU1 SMI control
4 CPU0 SMI control
5 DS4 LED control
6 DS2 LED control
7 (lsb) DS1 LED control
Memory Map
Page 28 of 115
R/W
na Unused
na Unused
0 = Using an ATX power supply
R
1 = Power obtained from a PCI slot
0 = U35 Switch 8 is ON
R
1 = U35 Switch 8 is OFF
0 = U30 Switch 8 is ON
R
1 = U30 Switch 8 is OFF
0 = PCI Host mode U24 Switch 6 is ON
R
1 = PCI Adapter mode U24 Switch 6 is OFF
0 = 8-bit Flash is at a higher address in memory, U24 Switch 6 is ON
R
1 = 8-bit SRAM is at a higher address in memory, U24 Switch 6 is ON
0 = Booted from 8-bit flash or SRAM U17 Switch 6 is ON
R
1 = Booted from 32-bit flash U17 Switch 6 is OFF
R/W
Asserts the Machine Check Pin (MCP) signal on CPU1
R/W
0 = CPU1 MCP signal not asserted
1 = CPU1 MCP signal asserted
Asserts the Machine Check Pin (MCP) signal on CPU0
R/W
0 = CPU0 MCP signal not asserted
1 = CPU0 MCP signal asserted
Controls the state of the timebase enable (TBEN) signal of both CPUs
R/W
0 = timebase runs freely on both CPUs
1 = timebase frozen on both CPUs
Asserts the System Management Interrupt signal on CPU1
R/W
0 = CPU1 SMI signal not asserted
1 = CPU1 SMI signal asserted
Asserts the System Management Interrupt signal on CPU0
R/W
0 = CPU0 SMI signal not asserted
1 = CPU0 SMI signal asserted
0 = DS4 LED is ON
R/W
1 = DS4 LED is OFF
0 = DS2 LED is ON
R/W
1 = DS2 LED is OFF
0 = DS1 LED is ON
R/W
1 = DS1 LED is OFF
Preliminary
Description
Description
750FXebm_ch3.fm
June 10, 2003