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PPC750FX

Evaluation Board

User's Manual
SA14-2720-00
Preliminary
June 10, 2003

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Summary of Contents for IBM PPC750FX

  • Page 1: Evaluation Board

    Title Page  PPC750FX Evaluation Board User’s Manual SA14-2720-00 Preliminary June 10, 2003...
  • Page 2 Without limiting the generality of the foregoing, any performance data contained in this document was determined in a specific or controlled environment and not submitted to any formal IBM test. Therefore, the results obtained in other operating environments may vary significantly. Under no circumstances will IBM be liable for any damages whatsoever arising out of or resulting from any use of the document or the information contained herein.
  • Page 3: Table Of Contents

    2.13.3 PPC750FX Voltages ........
  • Page 4 Evaluation Board Manual PPC750FX Evaluation Board Preliminary 4.2.3 Device Bank 2 Parameters (UARTs) ......... 34 4.2.4 Device Bank 3 Parameters (FRAM) .
  • Page 5 Evaluation Board Manual Preliminary PPC750FX Evaluation Board 11. CPLD Programming ..........73 11.1 Programming—Registers and Control Functions .
  • Page 6 Evaluation Board Manual PPC750FX Evaluation Board Preliminary Contents 750FXebmTOC.fm Page 6 of 115 June 10, 2003...
  • Page 7: Tables

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board Tables Table 2-1. Ethernet Ports ........................21 Table 2-2. Switch Settings ........................23 Table 2-3. Flash Configurations ......................23 Table 3-1. Board Address Space Usage ....................27 Table 3-2. Register0 ..........................27 Table 3-3.
  • Page 8 Evaluation Board Manual PPC750FX Evaluation Board Preliminary Table 10-7. PCI Connector Signals—J25 ....................59 Table 10-8. CPLD JTAG Connector—J26 ....................62 Table 10-9. Serial Port Connector Signals—J13, both ports ..............63 Table 10-10. System Controller Device Address Signals—J14 ..............64 Table 10-11. Memory Control Signals—J15 ....................66 Table 10-12.
  • Page 9: Figures

    Figure 1-1. PPC750FX Block Diagram ..................... 14 Figure 2-1. PPC750FX Board Architecture ....................19 Figure 2-2. Clock Distribution on the PPC750FX Board ................20 Figure 2-3. Board Ethernet Architecture ....................22 Figure 2-4. Board Serial Port Architecture ....................24 Figure 5-1.
  • Page 10 Evaluation Board Manual PPC750FX Evaluation Board Preliminary Figures 750FXebmLOF.fm Page 10 of 115 June 10, 2003...
  • Page 11: About This Book

    This manual describes an evaluation platform for the PPC750FX chip. Who Should Use This Book This book is written to aid programmers and other technical personnel in the use of the PPC750FX Evaluation Board. In order to use the board and this document, the reader shouldbe familiar with the following: •...
  • Page 12 Evaluation Board Manual PPC750FX Evaluation Board Preliminary Related Publications The following publications contain related information: • PowerPC 750FX RISC Microprocessor Embedded Controller Data Sheet • PowerPC 750FX RISC Microprocessor Embedded Controller Functional Specification • PowerPC 750FX RISC Microprocessor Embedded Controller User’s Manual •...
  • Page 13: Overview

    Warning: IBM is not responsible for use of the circuit designs on this board or use of the design of the board itself in any other applications. Any functional, reliability, or safety issues resulting from the use of any part of this board design, including copying the board, are the responsibility of the user.
  • Page 14: Figure 1-1. Ppc750Fx Block Diagram

    Enhanced with parity L2 Cache with ECC The PPC750FX processor has the following features: • Branch processing unit - Four instructions fetched per clock. - One branch processed per cycle (plus resolving two speculations). - Up to one speculative stream in execution, one additional speculative stream in fetch.
  • Page 15 Evaluation Board Manual Preliminary PPC750FX Evaluation Board • Decode - Register file access. - Forwarding control. - Partial instruction decode. • Load/Store unit - One cycle load or store cache access (byte, half word, word, double word). - Effective address generation.
  • Page 16 Evaluation Board Manual PPC750FX Evaluation Board Preliminary - Pseudo-LRU replacement. - Copy-back or write-through data cache (on a page per page basis). - Parity on L1 tags and arrays. - Three-state (MEI) memory coherency. - Hardware support for data coherency.
  • Page 17: Board Features

    - Powerful diagnostic and test interface through Common On-Chip Processor (COP) and IEEE 1149.1 (JTAG) interface. 1.2 Board Features The features of the PPC750FX evaluation board are summarized briefly below. More detail may be found in Section 2 Board Design on page 19. • PCI adapter form factor •...
  • Page 18 Evaluation Board Manual PPC750FX Evaluation Board Preliminary Overview 750FXebm_ch1.fm Page 18 of 115 June 10, 2003...
  • Page 19: Board Design

    SEEPROM 2.1 Processor The PPC750FX evaluation board is based upon the PPC750FX processor. See Section 1.1 PowerPC 750FX RISC Microprocessor Features on page 13 for details. There are two PPC750FX processors on this board. 750FXebm_ch2.fm Board Design June 10, 2003...
  • Page 20: Board Clocking

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary 2.2 Board Clocking The clock architecture of the PPC750FX board is illustrated in Figure 2-2. Figure 2-2. Clock Distribution on the PPC750FX Board External clock (see Note) MK74CB218 C9531AT 133MHz @ 2.5V CPU 0 133MHz @ 2.5V...
  • Page 21: Internal Processor Clocking

    2.6 PCI Bus This PPC750FX evaluation board is a full-length PCI card and is intended to be operated while plugged into a PCI slot in a personal computer or a PCI backplane. However, because an ATX power connector is provided, it can be operated without being plugged into a PCI slot.
  • Page 22: Flash Memory

    The following describes how to access Flash memory directly on the board. Eight-bit Flash memory is used on the PPC750FX board. No benchmarking impact is expected from the use of a narrow rather than a wide Flash array. For performance work, one should expect to replace the initial firmware support provided in the Flash with more optimized routines residing in DRAM.
  • Page 23: Table 2-2. Switch Settings

    The base addresses of peripherals attached to the MV64360 system controller device are software dependent. The values in the table above are used by the PPC750FX Evaluation Kit Software. Other software environments may use different values for the peripheral base addresses.
  • Page 24: Nvram

    UART provides four interface signals (Tx, Rx, DSR, DTR) and is connected to an RJ11/12 connector. Both serial ports are clocked by the same 3.68MHz oscillator provided on the board. The Multi-Protocol Serial Controllers in the system controller are not supported on the PPC750FX evaluation board.
  • Page 25: Logic Analyzer Connections

    These measurement points can also be used to connect external voltage supplies. Note: The 60x bus voltage supply to the PPC750FX can be +1.8V, +2.5V, or +3.3V. To use any voltage other than the +2.5V supplied by the board, the voltage must be supplied externally, and the 60x voltage selection signals to the PPC750FX must be programmed accordingly.
  • Page 26: Sdram Voltages

    2.14 Form Factor The PPC750FX board is a full-length PCI card intended to be plugged into and operated in a standard PCI slot on a personal computer or a PCI backplane. If a personal computer or PCI backplane are not available, it can operate stand-alone with an external ATX power supply connected at J34.
  • Page 27: Memory Map

    Note: The base addresses of peripherals attached to the MV64360 system controller device are software dependent. The values in the table above are used by the PPC750FX Evaluation Kit Software. Other software environments may use different values for the peripheral base addresses.
  • Page 28: Table 3-3. Register1

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary Table 3-3. Register1 Note: This register should be written before reading in order to latch the most current status. Any value can be written to the register. Name Description 0 (msb) Unused Unused...
  • Page 29: Table 3-5. Register3

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board Table 3-5. Register3 Name Description Five MPP/GPP pins on the system controller can be used to control the SRESET and HRESET of pins of the processors, and an entire board reset. To give software a chance to configure the MPP/GPP...
  • Page 30 Evaluation Board Manual PPC750FX Evaluation Board Preliminary Memory Map 750FXebm_ch3.fm Page 30 of 115 June 10, 2003...
  • Page 31: Programming The System Controller

    This section provides guidance on programming the system controller to agree with the board design. 4.1 DDR SDRAM The following are the characteristics of the DDR SDRAM memory on the PPC750FX evaluation board: Table 4-1. DDR SDRAM Characteristics Memory Type...
  • Page 32: Device Bank 0 Parameters (32-Bit Flash)

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary 4.2.1 Device Bank 0 Parameters (32-bit Flash) Table 4-2. Device Bank 0 Parameters = 0x85A492BF Field Value (bin) Comment Number of Sysclk cycles that the system controller does not drive the TurnOff address/data bus after completion of a device read...
  • Page 33: Device Bank 1 Parameters (Cpld Registers)

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 4.2.2 Device Bank 1 Parameters (CPLD registers) Table 4-3. Device Bank 1 Parameters = 0x8004921A Field Value (bin) Comment Number of Sysclk cycles that the system controller does not drive the TurnOff address/data bus after completion of a device read...
  • Page 34: Device Bank 2 Parameters (Uarts)

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary 4.2.3 Device Bank 2 Parameters (UARTs) Table 4-4. Device Bank 2 Parameters = 0x8C002BD6 Field Value (bin) Comment Number of Sysclk cycles that the system controller does not drive the TurnOff address/data bus after completion of a device read...
  • Page 35: Device Bank 3 Parameters (Fram)

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 4.2.4 Device Bank 3 Parameters (FRAM) Table 4-5. Device Bank 3 Parameters = 0x8D891445 Field Value (bin) Comment Number of Sysclk cycles that the system controller does not drive the TurnOff address/data bus after completion of a device read...
  • Page 36: Boot Device Parameters (8 Bit Flash And Sram)

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary 4.2.5 Boot Device Parameters (8 bit flash and SRAM) If booting from the 8-bit Flash or SRAM, the default value of the Boot Device Parameters register in the system controller is 0x8FCFFFFF. To improve the access time to the Flash contents, the register can be changed to the following: Table 4-6.
  • Page 37: Reset And Interrupts

    The system controller contains an interrupt controller that handles interrupts from peripherals inside the system controller as well as external peripherals. There are three external interrupt inputs to the PPC750FX (INT, MCP, and SMI). See Table 5-1 for more detail.
  • Page 38: Table 5-1. External Interrupts

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary Table 5-1. External Interrupts MPP Controller Pin +/- Active Sensitivity Description level UART Channel A level UART Channel B – level Ethernet PHY – level PCI Intr A – level PCI Intr B –...
  • Page 39: Switches

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 6. Switches This section shows the location of all the switches on the board, and explains the function of each switch. Table 6-1. Switches Location Function Page Reset pushbutton U17, U24 System controller initialization...
  • Page 40: Atx Power-On Pushbutton

    PS_ON Generates power-on signal to the external ATX power connector. 6.3 CPU 0 PLL Configuration An 8-position DIP switch at location U30 configures the PLL for the first PPC750FX processor (U1). Table 6-4. CPU 0 PLL Configuration—U30 Switch No. Signal...
  • Page 41: Cpu 1 Pll Configuration

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 6.4 CPU 1 PLL Configuration An 8-position DIP switch at location U35 configures PLL for the second PPC750FX processor (U2). Table 6-5. CPU 1 PLL Configuration Switches—U35 Switch No. Signal Default Setting Description (0 = ON = closed, 1= OFF = open)
  • Page 42: System Controller Initialization

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary 6.5 System Controller Initialization Two 8-position DIP switches at location U17 and U24 provide initilization settings for the system controller. Table 6-6. System Controller Initilization—U17 Switch No. Signal Default Setting Description (0 = ON = closed, 1 = OFF = open)
  • Page 43: Table 6-7. System Controller Initilization-U24

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board Table 6-7. System Controller Initilization—U24 Switch No. Signal Default Setting Description (0 = ON = closed, 1 = OFF = open) ON = DDR SDRAM address/control signals toggle on falling edge of DRAM clock.
  • Page 44 Evaluation Board Manual PPC750FX Evaluation Board Preliminary Switches 750FXebm_ch6.fm Page 44 of 115 June 10, 2003...
  • Page 45: Fuses, Batteries, Regulators, And Fans

    7.1.1 1.45V Supplies The PPC750FX uses +1.45 V for the logic and PLL voltages. There are two +1.45V supplies on the board. They are identified as VCCA1 and VCCA2. A pair of zero-ohm resistors can be removed for either of both supplies to create a connection point or points for current measurement or external supply connection.
  • Page 46: Supply

    7.1.2 2.5V Supply The PPC750FX uses 2.5V for the 60x bus. There is one 2.5V supply on the board. It is identified as VCCA3. A pair of zero-ohm resistors can be removed to create a connection point or points for current measurement or external supply connection.
  • Page 47: Displays

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 8. Displays There are nine LED displays on the board. Table 8-1 identifies the location, color and function of each display. Figure 8-1 shows the location on the board. Note: There are four Ethernet status LEDs integrated in the two-port Ethernet connector at J20. There are two LEDs per port which are physically located at the corners of each of the two sockets.
  • Page 48 Evaluation Board Manual PPC750FX Evaluation Board Preliminary Displays 750FXebm_ch8.fm Page 48 of 115 June 10, 2003...
  • Page 49: Jumpers

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 9. Jumpers The location, type, and function for all jumpers on the board are described in the following sections. Table 9-1. Jumpers Location Function Page 32-bit Flash write protection Ignore Fan PCI interrupt selection J27–J30...
  • Page 50: Write-Protect 32-Bit Flash

    9.2 Ignore Fan There is one fan on this board that cools both of the PPC750FX processor modules. The connector for the fan power provides a feedback signal to the CPLD indicating a properly functioning fan. When the jumper at J16 is installed, the fan is not monitored.
  • Page 51: Pci Interrupt Selection

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 9.3 PCI Interrupt Selection Jumper J22 configures the adapter mode PCI interrupt output from the system controller to one or more of the four PCI interface interrupts. This a 2x4 Berg type header.
  • Page 52 Evaluation Board Manual PPC750FX Evaluation Board Preliminary Jumpers 750FXebm_ch9.fm Page 52 of 115 June 10, 2003...
  • Page 53: Connectors

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 10. Connectors The location, type, function, and pin assignment for all board connections are described in the following sections. Connectors are listed in Table 10-1 and shown in Figure 10-1. Test connections are described in Section 10.12 and shown in Figure 10-13.
  • Page 54: Figure 10-1. Connector Location Diagram, Top Side

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary Figure 10-1. Connector Location Diagram, Top Side Keying slots Note: PCI contacts A1 through A94 mirror the B1-B94 contacts on the bottom side of the card. Connectors 750FXebm_ch10.fm Page 54 of 115 June 10, 2003...
  • Page 55: Auxiliary Power

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 10.1 Auxiliary Power The board is equipped with a standard ATX power connector. This allows the board to be externally powered from a standard ATX power supply when it is not installed in a PCI slot.
  • Page 56: Ground

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary 10.2 Ground Test points for grounding logic analyzers and other test equipment are available on these connectors. These are 1x1 Berg type connectors. Figure 10-3. Ground Connectors—J1, J2, J7, J9, J10, J12, J17, J18, J23, J24 Table 10-3.
  • Page 57: Riscwatch Jtag Debugger

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 10.4 RISCWatch JTAG Debugger The RISCWatch JTAG debugger connects to the board through a 2x8 header. Figure 10-5. RISCWatch JTAG Connector—J11 Table 10-5. RISCWatch Signals—J11 Signal Name unused TRST_N unused PWRSENSE unused unused...
  • Page 58: Ethernet

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary 10.5 Ethernet This board provides two Ethernet ports. The connections are through a single housing at J20 that contains two RJ45 connectors. Each connector contains integral magnetics and two LEDs. The ports are identified as 1 and 2.
  • Page 59: Pci Connector

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 10.6 PCI Connector This evaluation board is a PCI card. It has a standard PCI connector that plugs into a standard +3.3V or +5V PCI socket on a PC system board. The signals on the PCI conector are the standard set of PCI signals.
  • Page 60 Evaluation Board Manual PPC750FX Evaluation Board Preliminary Table 10-7. PCI Connector Signals—J25 (Continued) Signal Signal AD28 AD27 AD26 AD25 +3.3V AD24 C/BE3 IDSEL AD23 +3.3V AD22 AD21 AD20 AD19 +3.3V AD18 AD17 AD16 C/BE2 +3.3V FRAME IRDY +3.3V TRDY DEVSEL...
  • Page 61 Evaluation Board Manual Preliminary PPC750FX Evaluation Board Table 10-7. PCI Connector Signals—J25 (Continued) Signal Signal +3.3V (I/O) +3.3V (I/O) ACK64 REQ64 – – Key slot Key slot – – Reserved C/BE7 C/BE6 C/BE5 C/BE4 +3.3V(I/O) PAR64 AD63 AD62 AD61 +3.3V(I/O)
  • Page 62: Cpld Jtag Connector

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary Table 10-7. PCI Connector Signals—J25 (Continued) Signal Signal Reserved Reserved Reserved Reserved 10.7 CPLD JTAG Connector The CPLD may be programmed in place on the board via this JTAG connector and appropriate downloading software. This is a 2x5 Berg type connector.
  • Page 63: Serial Ports

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 10.8 Serial Ports Serial Port 1 (J13 Right) and Serial Port 2 (J13 Left) are provided through standard RJ11/12 connectors, as shown in Figure 10-9. Both serial port interfaces are provided by the ST16C2552 attached to the system controller and support only four RS-232 signals.
  • Page 64: System Controller Device Address Bus

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary 10.9 System Controller Device Address Bus Connection to HP logic analyzers via HP E5346A High Density Probe Adapters is provided by board mounted connectors, Mictor Part Number 2-767004-2. This connector provides user access to the system controller peripheral address bus for test and debug purposes.
  • Page 65 Evaluation Board Manual Preliminary PPC750FX Evaluation Board Table 10-10. System Controller Device Address Signals—J14 (Continued) Analyzer Signal Name addr_pod1 – D7 DEV_ADR(7) addr_pod0 – D6 DEV_ADR(22) addr_pod1 – D6 DEV_ADR(6) addr_pod0 – D5 DEV_ADR(21) addr_pod1 – D5 DEV_ADR(5) addr_pod0 – D4 DEV_ADR(20) addr_pod1 –...
  • Page 66: Memory Control

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary 10.10 Memory Control Connection to HP logic analyzers via HP E5346A High Density Probe Adapters is provided by board mounted connectors, Mictor Part Number 2-767004-2. This connector carries the burst address bus and the chip select signals from the system controller.
  • Page 67 Evaluation Board Manual Preliminary PPC750FX Evaluation Board Table 10-11. Memory Control Signals—J15 (Continued) Analyzer Signal Name cntl_pod1 – D7 CPU0_HRESET_2.5_N cntl_pod0 – D6 NVRAM_CS_N cntl_pod1 – D6 CPU0_SRESET_2.5_N cntl_pod0 – D5 BIG_FLASH_CS_N cntl_pod1 – D5 unused cntl_pod0 – D4 SMALL_FLASH_HI_CS_N cntl_pod1 –...
  • Page 68: External Clock Input

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary 10.11 External Clock Input An external 133MHz board clock may be provided by an external oscillator connected to this board-mounted SMA connector. The oscillator output should have 3.3V logic levels. The input impedance to this connector is approximately 50 Ω...
  • Page 69: Test Connections

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 10.12 Test Connections Access to selected points in the board circuits, not available through connectors or jumpers, is provided by small test connections. All of the test connections are small pads with a center hole. An electrical connection can be made to any of these test connections for test purposes.
  • Page 70 Evaluation Board Manual PPC750FX Evaluation Board Preliminary Table 10-13. Test Connections (Continued) Location Component Signal TP23 U3 System Controller MPP3 TP24 U3 System Controller MPP2 TP25 U3 System Controller MPP1 TP27 U3 System Controller MPP6 TP28 U3 System Controller MPP4...
  • Page 71: Figure 10-13. Test Connection Locations

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board Figure 10-13. Test Connection Locations TP2 TP1 TP6 TP7 TP12 TP16 TP15 TP20 TP17 TP22 TP11 TP14 TP19 TP10 TP21 TP23 TP13 TP18 TP24 TP41* TP25 TP36 TP33 TP27 TP31 TP42* TP28 TP32...
  • Page 72 Evaluation Board Manual PPC750FX Evaluation Board Preliminary Connectors 750FXebm_ch10.fm Page 72 of 115 June 10, 2003...
  • Page 73: Cpld Programming

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 11. CPLD Programming This chapter contains logic of the CPLD (formerly FPGA) module and timing values for the signals associated with the CPLD. Table 11-1. Section Contents Description Page Programming—Registers and Control Functions Timing—Registers and Control Functions...
  • Page 74 Evaluation Board Manual PPC750FX Evaluation Board Preliminary Table 11-2. CPLD I/O Pin List (Continued) Name Function ~TMS~ Input write_n Output uart_cs_n Output VCCIO1 Power nvram_cs_n Output led1 Output led_red_n Output ignore_fans_n Input mpp0_sreset_n Input cpu1_chkstop_n Input sysreset Output dev_adr[5] Bidir...
  • Page 75 Evaluation Board Manual Preliminary PPC750FX Evaluation Board Table 11-2. CPLD I/O Pin List (Continued) Name Function cpu0_hreset_n Output cpu_trst_n Output cpu1_sreset_n Output cpu1_hreset_n Output cpu0_sreset_n Output lcs_n[1] Input mpp_reset_out_n Input ~VREFB~ Input atx_ok_n Input ~TCK~ Input dev_we_n[0] Input lcs_n[0] Input...
  • Page 76: Cpld Logic

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary Table 11-2. CPLD I/O Pin List (Continued) Name Function GND+ pld25mhz Input VCCINT Power dev_adr[0] Bidir dev_adr[1] Bidir dev_adr[2] Bidir dev_adr[3] Bidir dev_adr[4] Bidir ldev_addr[20] Input cpufan_ok_n Input ldev_addr[19] Input 11.1.2 CPLD Logic The folllowing sections provided a representation of the logic of the complete CPLD in either graphical or code listing format.
  • Page 77: Top Level Block Diagram 1

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 11.1.2.1 Top Level Block Diagram 1 framcs badr0 nvram_burst_cs_n badr0 nvram_burst_cs_n badr1 badr1 badr2 badr2 pld_sysclk sysclock sysreset_n sysreset lcs_n3 lcs_n[3] cstiming_n cstiming_n inst4 decode_block sysreset_n small_flash_cs_n sysreset_n small_flash_lo_cs_n PLD_SYSCLK small_flash_hi_cs_n sysclk small_flash_hi_cs_n...
  • Page 78: Top Level Block Diagram 2

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary 11.1.2.2 Top Level Block Diagram 2 reset_block pld25mhz pci_reset_n 25Mclk pci_reset_n rw_hreset sysreset_n rw_hreset sysreset_n rw_sreset cpu0_hreset_n rw_sreset cpu0_hreset_n rw_trst cpu0_sreset_n rw_trst cpu0_sreset_n mpp_reset_2ms_n cpu1_hreset_n mpp_reset_2ms_n cpu1_hreset_n mpp0_hreset_n cpu1_sreset_n mpp0_hreset_n cpu1_sreset_n mpp0_sreset_n cpu_trst_n...
  • Page 79: Framcs Logic

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 11.1.2.3 framcs Logic The following logic diagram defines the function of the logic in the framcs part of the CPLD: Date: May 6, 2003 framcs.bdf Project: top lpm_dff0 badr0 INPUT qadr0 data clock...
  • Page 80: Decode_Block Program

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary 11.1.2.4 decode_block Program The following code listing defines the function of the logic in the decode_block part of the CPLD: INCLUDE "lpm_ff.inc"; -- 10:30 AM Mar 26, 2003 INCLUDE "lpm_counter.inc"; SUBDESIGN decode_block sysreset_n : INPUT;...
  • Page 81 Evaluation Board Manual Preliminary PPC750FX Evaluation Board FLASH/SRAM/BIG : NODE; -- boot from SRAM BIG/SRAM/FLASH : NODE; -- boot BIG, then SRAM, flash on CS0 BIG/FLASH/SRAM : NODE; -- boot BIG, then flash, SRAM on CS0 halfclk : NODE; sram_cs_n : NODE;...
  • Page 82 Evaluation Board Manual PPC750FX Evaluation Board Preliminary del_nvramcs.data[3] = del_nvramcs.q[2]; del_nvramcs.data[4] = del_nvramcs.q[3]; del_nvramcs.data[5] = del_nvramcs.q[4]; del_nvramcs.data[6] = del_nvramcs.q[5]; del_nvramcs.data[7] = del_nvramcs.q[6]; del_nvramcs.data[8] = del_nvramcs.q[7]; del_nvramcs.data[9] = del_nvramcs.q[8]; nvram_cs_n = del_nvramcs.q[4] # (!del_nvramcs.q[9] & !writeNVRAM_n) # nvram_burst_cs_n; !WriteNVRAM_n =!CSTiming_n & !LDevR_W_n;...
  • Page 83 Evaluation Board Manual Preliminary PPC750FX Evaluation Board !sram_lo_cs_n = (!CSTiming_n & ((FLASH/SRAM/BIG & loarea) #(BIG/FLASH/SRAM & lowerarea) #(SRAM/FLASH/BIG & bootarea) #(BIG/SRAM/FLASH & botarea))); !big_flash_cs_n = (!CSTiming_n & ((!bootsmall_n & !lcs_n[0]) # ( bootsmall_n & !lbootcs_n))); sram_cs_n =sram_hi_cs_n & sram_lo_cs_n; !Read_n =!CSTiming_n &...
  • Page 84: Registers2 Program

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary 11.1.2.5 registers2 Program The following code listing defines the function of the logic in the registers2 part of the CPLD: INCLUDE "lpm_ff.inc"; INCLUDE "lpm_mux.inc"; SUBDESIGN registers2 sysreset_n : INPUT; cstiming_n : INPUT; we_n0 : INPUT;...
  • Page 85 Evaluation Board Manual Preliminary PPC750FX Evaluation Board Register1 : lpm_ff WITH ( LPM_WIDTH = 8, LPM_FFTYPE = "DFF" Register2_sel : NODE;-- register 2 Register2 : lpm_ff WITH ( LPM_WIDTH = 8, LPM_FFTYPE = "DFF" Register3_sel : NODE;-- register 3 Register3 : lpm_ff WITH ( LPM_WIDTH = 8, LPM_FFTYPE = "DFF"...
  • Page 86 Evaluation Board Manual PPC750FX Evaluation Board Preliminary ldev_adr[8..3] = lpm_ff_component.q[7..2]; -- latched control signals ldevR_W_n = lpm_ff_component.q[1]; -- read or write cycle lboot_cs_n = lpm_ff_component.q[0] # cstiming_n; -- on board flash bank 0 -- all accesses to PLD registers are assumed to be 8-bit hw wise.
  • Page 87 Evaluation Board Manual Preliminary PPC750FX Evaluation Board cpu0_smi_n = cpu0_smi_n_node; -- cpu1_smi_n = cpu1_smi_n_node; -- cpu_tben = cpu_tben_node; -- cpu_mcp0 = cpu_mcp0_node; -- cpu_mcp1 = cpu_mcp1_node; -- -- Register3, Write/Read Register3.enable = Register3_sel & !ldevR_W_n; Register3.aclr = !sysreset_n; -- !sysreset_n = 1 in reset, clears the output Register3.clock = we_n0;...
  • Page 88 Evaluation Board Manual PPC750FX Evaluation Board Preliminary -- Register 4 if ((badr[2..0] == B"100")) then BoardRev_sel = !fpga_cs_n; data_sel[] = 4; else BoardRev_sel = gnd; end if; -- read logic bux_muxer.data[0][7..0] = PLDversion[7..0]; bux_muxer.data[1][7..0] = Register1.q[7..0]; bux_muxer.data[2][7..0] = Register2.q[7..0]; bux_muxer.data[3][7..0] = Register3.q[7..0];...
  • Page 89: Reset_Block Program

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 11.1.2.6 reset_block Program The following code listing defines the function of the logic in the reset_block part of the CPLD: INCLUDE "lpm_ff.inc"; SUBDESIGN reset_block 25Mclk : INPUT; rw_hreset : INPUT; rw_sreset : INPUT;...
  • Page 90 Evaluation Board Manual PPC750FX Evaluation Board Preliminary cpu_trst_n_ : NODE; cpu0_hreset_n_ : NODE; cpu0_sreset_n_ : NODE; cpu1_hreset_n_ : NODE; cpu1_sreset_n_ : NODE; del_sysreset_n : NODE; del_sysreset_n_ : lpm_ff WITH ( LPM_WIDTH = 8, LPM_FFTYPE = "DFF" del_pgd : NODE; del_pgd_ : lpm_ff WITH ( LPM_WIDTH = 8, LPM_FFTYPE = "DFF"...
  • Page 91 Evaluation Board Manual Preliminary PPC750FX Evaluation Board -- Cascade tff’s - create a 2 bit counter -- that runs at the full rate. AND the output bits together -- and whenever count = "11" a pulse is generated. -- Use that 1/4 rate pulse as an enable for the dff’s.
  • Page 92 Evaluation Board Manual PPC750FX Evaluation Board Preliminary del_rw_sreset[1].d = del_rw_sreset[0].q; cpu0_sreset_n_ = (del_rw_sreset[0].q & del_rw_sreset[1].q) & (mpp0_sreset_n # !mpp_block_n); above line: if mpp_block_n is 1 then allow mpp0_sreset# through. cpu0_sreset_n = cpu0_sreset_n_; cpu1_sreset_n_ = (del_rw_sreset[0].q & del_rw_sreset[1].q) & (mpp1_sreset_n # !mpp_block_n);...
  • Page 93: Misc Logic

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 11.1.2.7 misc Logic The following logic diagram defines the function of the logic in the misc part of the CPLD: LPM_COUNTER LPM_COMPARE cnt_en dataa[] pld25mhz pld25mhz INPUT datab[] aneb mpp_reset_out_n LCELL mpp_reset_out_n INPUT...
  • Page 94: Timing-Registers And Control Functions

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary 11.2 Timing—Registers and Control Functions The timing data in the following tables are based on simulation. 11.2.1 Maximum Clock Frequency Table 11-4 provides the actual frequency at which the indicated clock is running, and the highest frequency at which it can be allowed to run before the period becomes shorter than the worst case signal propagation time.
  • Page 95 Evaluation Board Manual Preliminary PPC750FX Evaluation Board Table 11-5. Clock-to-Output Time (Continued) Output Signal Clock Longest Delay (ns) Shortest Delay (ns) dev_adr[2] dev_we_n[0] 9.400 9.400 dev_adr[3] 12.500 12.500 dev_adr[3] dev_we_n[0] 9.400 9.400 dev_adr[4] 12.500 12.500 dev_adr[4] dev_we_n[0] 9.400 9.400 dev_adr[5] 12.500...
  • Page 96: Pin-To-Pin Signal Delay

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary 11.2.3 Pin-to-Pin Signal Delay Table 11-6 provides the input pin-to-output pin delay time for all signals that are not clocked through a register. Table 11-6. Pin-to-Pin Signal Delay Source Destination Longest Delay (ns)
  • Page 97 Evaluation Board Manual Preliminary PPC750FX Evaluation Board Table 11-6. Pin-to-Pin Signal Delay (Continued) Source Destination Longest Delay (ns) Shortest Delay (ns) badr[2] dev_adr[5] 8.700 5.600 badr[2] dev_adr[6] 8.700 5.600 badr[2] dev_adr[7] 8.700 5.600 badr[2] nvram_cs_n 14.700 14.700 badr[2] uart_cs_n 7.100 5.600...
  • Page 98 Evaluation Board Manual PPC750FX Evaluation Board Preliminary Table 11-6. Pin-to-Pin Signal Delay (Continued) Source Destination Longest Delay (ns) Shortest Delay (ns) flash_n/sram_sel small_flash_cs_n 5.300 5.300 flash_n/sram_sel small_flash_hi_cs_n 5.300 5.300 flash_n/sram_sel sram_cs_n 5.300 5.300 flash_n/sram_sel sram_hi_cs_n 5.300 5.300 flash_n/sram_sel textpin_d 5.500 5.500...
  • Page 99 Evaluation Board Manual Preliminary PPC750FX Evaluation Board Table 11-6. Pin-to-Pin Signal Delay (Continued) Source Destination Longest Delay (ns) Shortest Delay (ns) ldev_addr[20] sram_cs_n 5.200 5.200 ldev_addr[20] sram_hi_cs_n 5.200 5.200 ldev_addr[20] textpin_d 5.400 5.400 mpp0_hreset_n cpu0_hreset_n 10.600 10.200 mpp0_sreset_n cpu0_sreset_n 10.200 10.200...
  • Page 100: Setup And Hold Time

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary 11.2.4 Setup and Hold Time Table 11-7 provides the minimum setup and hold time for the indicated input relative to the indicated clock. Table 11-7. Setup and Hold Time Input Clock Setup Time (ns)
  • Page 101: Bills Of Materials

    Table 12-5, the component is not assembled if the DNP column contains TRUE. In some cases installation of DNP parts requires the removal of installed parts and constitutes a change in the design of the board. IBM does not support boards that have been modified by removing normally installed parts.
  • Page 102: Table 12-2. Component Placement Data Description

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary Figure 12-1. Example of a Component Placement List in the Schematics 7830 4260 7995 1355 1135 11130 6330 11120 The information provided in each column of the component placement table is described in Table 12-2: Table 12-2.
  • Page 103: Figure 12-2. Board Location Grid-Top View

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board The normal procedure to locate a component is to look up the coordinates in the Component Placement table in the schematic diagram, then use the X and Y scales on the edge of the board to get to the approximate location of the component on the board.
  • Page 104: Debugging Tools

    Evaluation Board Manual PPC750FX Evaluation Board Preliminary 12.2 Debugging Tools Table 12-3 identifies components that are recommended as aids for hardware monitoring. None of these components are shipped in the board package. Table 12-3. Debugging Tools Quantity Description 184 Pin DIMM Analysis Probe Vendor 1: FuturePlus Inc.
  • Page 105: Board Bill Of Materials

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board 12.4 Board Bill of Materials Table 12-5 provides a complete list of all components used to manufacture the board assembly. In addition, all components that appear in the schematics but that are not actually assembled on the board (DNP column contains TRUE) appear in this table.
  • Page 106: Table 12-5. Evaluation Board Bill Of Materials

    Table 12-5. Evaluation Board Bill of Materials Value Ref Des JEDEC Type Vendor Vendor PN ALT1 Vendor ALT1 Vendor PN ALT2 Vendor ALT2 Vendor PN C1-C5, C43, C66, C67, C69- SMEC2816R SPRAGUE 293D336X0020D2 NRD336M20RBM AVX TAJD336M020R C71, C75, C78, C81, C82, C98-C101, C242, C283, C493, C496, C498 0.1U_10V 385...
  • Page 107 Table 12-5. Evaluation Board Bill of Materials (Continued) Value Ref Des JEDEC Type Vendor Vendor PN ALT1 Vendor ALT1 Vendor PN ALT2 Vendor ALT2 Vendor PN 2.2U C183, C209, C352, C379 SMC0805R TAIYO YUDEN CEJMK212BJ225K C2012X5R0J225 MURATA GRM21BR60J22 KT000N 5KC01L 0.001U C74, C85, C92, C185 SMEC0603...
  • Page 108 Table 12-5. Evaluation Board Bill of Materials (Continued) Value Ref Des JEDEC Type Vendor Vendor PN ALT1 Vendor ALT1 Vendor PN ALT2 Vendor ALT2 Vendor PN 70@100 L27, L29 SMC1206R MURATA BLM31AF700SN1 3.3U D03316 COILCRAFT D03316P-332HC PULSE_ENG P0751.332T GOWANDA SMP3316-331M | 60@100 SMC1210 HF50ACB-322513-...
  • Page 109 Table 12-5. Evaluation Board Bill of Materials (Continued) Value Ref Des JEDEC Type Vendor Vendor PN ALT1 Vendor ALT1 Vendor PN ALT2 Vendor ALT2 Vendor PN 1.0K R116, R237, R308, R309, SMER0402 PANASONIC ERJ2RKF1001X PHYCOMP 9C1A04021001F R332, R352, R424, R426, LHF3 R427, R431, R438, R444, R445, R447, R450, R520,...
  • Page 110 ALT1 Vendor ALT1 Vendor PN ALT2 Vendor ALT2 Vendor PN TP1-TP3, TP6-TP9, TP11- TP014 DO NOT ORDER DO NOT ORDER TP25, TP27-TP39, TP41-TP43 750FXUPPER PPC750FX- GB2533T 256MBIT U10, U11, U13, U14, U44, TSOP2_66P65 INFINEON HYB25D256160BT _16KX16 U45, U47, U48 256MBIT...
  • Page 111 Table 12-5. Evaluation Board Bill of Materials (Continued) Value Ref Des JEDEC Type Vendor Vendor PN ALT1 Vendor ALT1 Vendor PN ALT2 Vendor ALT2 Vendor PN QFPE100RP6 BROADCOM BCM5222KQM C9531AT TSSOP28_P65 IMI C9531AT IMI9531CT 221789-1 SOT223A DALLAS DS1233AZ-10 SEMICONDUCT U6, U41 TSOP56P5 INTEL E28F128J3A-150...
  • Page 112 Table 12-5. Evaluation Board Bill of Materials (Continued) Value Ref Des JEDEC Type Vendor Vendor PN ALT1 Vendor ALT1 Vendor PN ALT2 Vendor ALT2 Vendor PN TRUE J31-J33 HDR1X3_MTA 640452-3 TRUE HEADER J37-J39 HDR_4X1_100 MILL-MAX 800-10-004-10-001 DIGIKEY ED7204-ND _4_VERT TRUE R63, R84, R119, R225, R228, SMER0402 PANASONIC...
  • Page 113: Index

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board Index registers and control timing auxiliary materials clock-to-output pin-topin signal delay registers and control setup and hold time CPLD register definitions batteries bill of materials processor support auxiliary material in kit current monitoring...
  • Page 114 Evaluation Board Manual PPC750FX Evaluation Board Preliminary non-volatile RAM overview connector real-time clock regulators resets serial ports switches ATX power-on pushbutton PLL 0 configuration PLL 1 configuration reset pushbutton system controller initialization system controller SDRAM sytem controller peripheral bank register settings...
  • Page 115: Revision Log

    Evaluation Board Manual Preliminary PPC750FX Evaluation Board Revision Log Revision Date Contents of Modification 06/10/03 Initial creation of the book. 750FXebm_revlog.fm Revision Log June 10, 2003 Page 115 of 115...

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