Title Page PPC750FX Evaluation Board User’s Manual SA14-2720-00 Preliminary June 10, 2003...
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Without limiting the generality of the foregoing, any performance data contained in this document was determined in a specific or controlled environment and not submitted to any formal IBM test. Therefore, the results obtained in other operating environments may vary significantly. Under no circumstances will IBM be liable for any damages whatsoever arising out of or resulting from any use of the document or the information contained herein.
This manual describes an evaluation platform for the PPC750FX chip. Who Should Use This Book This book is written to aid programmers and other technical personnel in the use of the PPC750FX Evaluation Board. In order to use the board and this document, the reader shouldbe familiar with the following: •...
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Evaluation Board Manual PPC750FX Evaluation Board Preliminary Related Publications The following publications contain related information: • PowerPC 750FX RISC Microprocessor Embedded Controller Data Sheet • PowerPC 750FX RISC Microprocessor Embedded Controller Functional Specification • PowerPC 750FX RISC Microprocessor Embedded Controller User’s Manual •...
Warning: IBM is not responsible for use of the circuit designs on this board or use of the design of the board itself in any other applications. Any functional, reliability, or safety issues resulting from the use of any part of this board design, including copying the board, are the responsibility of the user.
Enhanced with parity L2 Cache with ECC The PPC750FX processor has the following features: • Branch processing unit - Four instructions fetched per clock. - One branch processed per cycle (plus resolving two speculations). - Up to one speculative stream in execution, one additional speculative stream in fetch.
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Evaluation Board Manual Preliminary PPC750FX Evaluation Board • Decode - Register file access. - Forwarding control. - Partial instruction decode. • Load/Store unit - One cycle load or store cache access (byte, half word, word, double word). - Effective address generation.
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Evaluation Board Manual PPC750FX Evaluation Board Preliminary - Pseudo-LRU replacement. - Copy-back or write-through data cache (on a page per page basis). - Parity on L1 tags and arrays. - Three-state (MEI) memory coherency. - Hardware support for data coherency.
- Powerful diagnostic and test interface through Common On-Chip Processor (COP) and IEEE 1149.1 (JTAG) interface. 1.2 Board Features The features of the PPC750FX evaluation board are summarized briefly below. More detail may be found in Section 2 Board Design on page 19. • PCI adapter form factor •...
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Evaluation Board Manual PPC750FX Evaluation Board Preliminary Overview 750FXebm_ch1.fm Page 18 of 115 June 10, 2003...
SEEPROM 2.1 Processor The PPC750FX evaluation board is based upon the PPC750FX processor. See Section 1.1 PowerPC 750FX RISC Microprocessor Features on page 13 for details. There are two PPC750FX processors on this board. 750FXebm_ch2.fm Board Design June 10, 2003...
Evaluation Board Manual PPC750FX Evaluation Board Preliminary 2.2 Board Clocking The clock architecture of the PPC750FX board is illustrated in Figure 2-2. Figure 2-2. Clock Distribution on the PPC750FX Board External clock (see Note) MK74CB218 C9531AT 133MHz @ 2.5V CPU 0 133MHz @ 2.5V...
2.6 PCI Bus This PPC750FX evaluation board is a full-length PCI card and is intended to be operated while plugged into a PCI slot in a personal computer or a PCI backplane. However, because an ATX power connector is provided, it can be operated without being plugged into a PCI slot.
The following describes how to access Flash memory directly on the board. Eight-bit Flash memory is used on the PPC750FX board. No benchmarking impact is expected from the use of a narrow rather than a wide Flash array. For performance work, one should expect to replace the initial firmware support provided in the Flash with more optimized routines residing in DRAM.
The base addresses of peripherals attached to the MV64360 system controller device are software dependent. The values in the table above are used by the PPC750FX Evaluation Kit Software. Other software environments may use different values for the peripheral base addresses.
UART provides four interface signals (Tx, Rx, DSR, DTR) and is connected to an RJ11/12 connector. Both serial ports are clocked by the same 3.68MHz oscillator provided on the board. The Multi-Protocol Serial Controllers in the system controller are not supported on the PPC750FX evaluation board.
These measurement points can also be used to connect external voltage supplies. Note: The 60x bus voltage supply to the PPC750FX can be +1.8V, +2.5V, or +3.3V. To use any voltage other than the +2.5V supplied by the board, the voltage must be supplied externally, and the 60x voltage selection signals to the PPC750FX must be programmed accordingly.
2.14 Form Factor The PPC750FX board is a full-length PCI card intended to be plugged into and operated in a standard PCI slot on a personal computer or a PCI backplane. If a personal computer or PCI backplane are not available, it can operate stand-alone with an external ATX power supply connected at J34.
Note: The base addresses of peripherals attached to the MV64360 system controller device are software dependent. The values in the table above are used by the PPC750FX Evaluation Kit Software. Other software environments may use different values for the peripheral base addresses.
Evaluation Board Manual PPC750FX Evaluation Board Preliminary Table 3-3. Register1 Note: This register should be written before reading in order to latch the most current status. Any value can be written to the register. Name Description 0 (msb) Unused Unused...
Evaluation Board Manual Preliminary PPC750FX Evaluation Board Table 3-5. Register3 Name Description Five MPP/GPP pins on the system controller can be used to control the SRESET and HRESET of pins of the processors, and an entire board reset. To give software a chance to configure the MPP/GPP...
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Evaluation Board Manual PPC750FX Evaluation Board Preliminary Memory Map 750FXebm_ch3.fm Page 30 of 115 June 10, 2003...
This section provides guidance on programming the system controller to agree with the board design. 4.1 DDR SDRAM The following are the characteristics of the DDR SDRAM memory on the PPC750FX evaluation board: Table 4-1. DDR SDRAM Characteristics Memory Type...
Evaluation Board Manual PPC750FX Evaluation Board Preliminary 4.2.1 Device Bank 0 Parameters (32-bit Flash) Table 4-2. Device Bank 0 Parameters = 0x85A492BF Field Value (bin) Comment Number of Sysclk cycles that the system controller does not drive the TurnOff address/data bus after completion of a device read...
Evaluation Board Manual Preliminary PPC750FX Evaluation Board 4.2.2 Device Bank 1 Parameters (CPLD registers) Table 4-3. Device Bank 1 Parameters = 0x8004921A Field Value (bin) Comment Number of Sysclk cycles that the system controller does not drive the TurnOff address/data bus after completion of a device read...
Evaluation Board Manual PPC750FX Evaluation Board Preliminary 4.2.3 Device Bank 2 Parameters (UARTs) Table 4-4. Device Bank 2 Parameters = 0x8C002BD6 Field Value (bin) Comment Number of Sysclk cycles that the system controller does not drive the TurnOff address/data bus after completion of a device read...
Evaluation Board Manual Preliminary PPC750FX Evaluation Board 4.2.4 Device Bank 3 Parameters (FRAM) Table 4-5. Device Bank 3 Parameters = 0x8D891445 Field Value (bin) Comment Number of Sysclk cycles that the system controller does not drive the TurnOff address/data bus after completion of a device read...
Evaluation Board Manual PPC750FX Evaluation Board Preliminary 4.2.5 Boot Device Parameters (8 bit flash and SRAM) If booting from the 8-bit Flash or SRAM, the default value of the Boot Device Parameters register in the system controller is 0x8FCFFFFF. To improve the access time to the Flash contents, the register can be changed to the following: Table 4-6.
The system controller contains an interrupt controller that handles interrupts from peripherals inside the system controller as well as external peripherals. There are three external interrupt inputs to the PPC750FX (INT, MCP, and SMI). See Table 5-1 for more detail.
Evaluation Board Manual Preliminary PPC750FX Evaluation Board 6. Switches This section shows the location of all the switches on the board, and explains the function of each switch. Table 6-1. Switches Location Function Page Reset pushbutton U17, U24 System controller initialization...
PS_ON Generates power-on signal to the external ATX power connector. 6.3 CPU 0 PLL Configuration An 8-position DIP switch at location U30 configures the PLL for the first PPC750FX processor (U1). Table 6-4. CPU 0 PLL Configuration—U30 Switch No. Signal...
Evaluation Board Manual Preliminary PPC750FX Evaluation Board 6.4 CPU 1 PLL Configuration An 8-position DIP switch at location U35 configures PLL for the second PPC750FX processor (U2). Table 6-5. CPU 1 PLL Configuration Switches—U35 Switch No. Signal Default Setting Description (0 = ON = closed, 1= OFF = open)
Evaluation Board Manual PPC750FX Evaluation Board Preliminary 6.5 System Controller Initialization Two 8-position DIP switches at location U17 and U24 provide initilization settings for the system controller. Table 6-6. System Controller Initilization—U17 Switch No. Signal Default Setting Description (0 = ON = closed, 1 = OFF = open)
7.1.1 1.45V Supplies The PPC750FX uses +1.45 V for the logic and PLL voltages. There are two +1.45V supplies on the board. They are identified as VCCA1 and VCCA2. A pair of zero-ohm resistors can be removed for either of both supplies to create a connection point or points for current measurement or external supply connection.
7.1.2 2.5V Supply The PPC750FX uses 2.5V for the 60x bus. There is one 2.5V supply on the board. It is identified as VCCA3. A pair of zero-ohm resistors can be removed to create a connection point or points for current measurement or external supply connection.
Evaluation Board Manual Preliminary PPC750FX Evaluation Board 8. Displays There are nine LED displays on the board. Table 8-1 identifies the location, color and function of each display. Figure 8-1 shows the location on the board. Note: There are four Ethernet status LEDs integrated in the two-port Ethernet connector at J20. There are two LEDs per port which are physically located at the corners of each of the two sockets.
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Evaluation Board Manual PPC750FX Evaluation Board Preliminary Displays 750FXebm_ch8.fm Page 48 of 115 June 10, 2003...
Evaluation Board Manual Preliminary PPC750FX Evaluation Board 9. Jumpers The location, type, and function for all jumpers on the board are described in the following sections. Table 9-1. Jumpers Location Function Page 32-bit Flash write protection Ignore Fan PCI interrupt selection J27–J30...
9.2 Ignore Fan There is one fan on this board that cools both of the PPC750FX processor modules. The connector for the fan power provides a feedback signal to the CPLD indicating a properly functioning fan. When the jumper at J16 is installed, the fan is not monitored.
Evaluation Board Manual Preliminary PPC750FX Evaluation Board 9.3 PCI Interrupt Selection Jumper J22 configures the adapter mode PCI interrupt output from the system controller to one or more of the four PCI interface interrupts. This a 2x4 Berg type header.
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Evaluation Board Manual PPC750FX Evaluation Board Preliminary Jumpers 750FXebm_ch9.fm Page 52 of 115 June 10, 2003...
Evaluation Board Manual Preliminary PPC750FX Evaluation Board 10. Connectors The location, type, function, and pin assignment for all board connections are described in the following sections. Connectors are listed in Table 10-1 and shown in Figure 10-1. Test connections are described in Section 10.12 and shown in Figure 10-13.
Evaluation Board Manual PPC750FX Evaluation Board Preliminary Figure 10-1. Connector Location Diagram, Top Side Keying slots Note: PCI contacts A1 through A94 mirror the B1-B94 contacts on the bottom side of the card. Connectors 750FXebm_ch10.fm Page 54 of 115 June 10, 2003...
Evaluation Board Manual Preliminary PPC750FX Evaluation Board 10.1 Auxiliary Power The board is equipped with a standard ATX power connector. This allows the board to be externally powered from a standard ATX power supply when it is not installed in a PCI slot.
Evaluation Board Manual PPC750FX Evaluation Board Preliminary 10.2 Ground Test points for grounding logic analyzers and other test equipment are available on these connectors. These are 1x1 Berg type connectors. Figure 10-3. Ground Connectors—J1, J2, J7, J9, J10, J12, J17, J18, J23, J24 Table 10-3.
Evaluation Board Manual PPC750FX Evaluation Board Preliminary 10.5 Ethernet This board provides two Ethernet ports. The connections are through a single housing at J20 that contains two RJ45 connectors. Each connector contains integral magnetics and two LEDs. The ports are identified as 1 and 2.
Evaluation Board Manual Preliminary PPC750FX Evaluation Board 10.6 PCI Connector This evaluation board is a PCI card. It has a standard PCI connector that plugs into a standard +3.3V or +5V PCI socket on a PC system board. The signals on the PCI conector are the standard set of PCI signals.
Evaluation Board Manual PPC750FX Evaluation Board Preliminary Table 10-7. PCI Connector Signals—J25 (Continued) Signal Signal Reserved Reserved Reserved Reserved 10.7 CPLD JTAG Connector The CPLD may be programmed in place on the board via this JTAG connector and appropriate downloading software. This is a 2x5 Berg type connector.
Evaluation Board Manual Preliminary PPC750FX Evaluation Board 10.8 Serial Ports Serial Port 1 (J13 Right) and Serial Port 2 (J13 Left) are provided through standard RJ11/12 connectors, as shown in Figure 10-9. Both serial port interfaces are provided by the ST16C2552 attached to the system controller and support only four RS-232 signals.
Evaluation Board Manual PPC750FX Evaluation Board Preliminary 10.9 System Controller Device Address Bus Connection to HP logic analyzers via HP E5346A High Density Probe Adapters is provided by board mounted connectors, Mictor Part Number 2-767004-2. This connector provides user access to the system controller peripheral address bus for test and debug purposes.
Evaluation Board Manual PPC750FX Evaluation Board Preliminary 10.10 Memory Control Connection to HP logic analyzers via HP E5346A High Density Probe Adapters is provided by board mounted connectors, Mictor Part Number 2-767004-2. This connector carries the burst address bus and the chip select signals from the system controller.
Evaluation Board Manual PPC750FX Evaluation Board Preliminary 10.11 External Clock Input An external 133MHz board clock may be provided by an external oscillator connected to this board-mounted SMA connector. The oscillator output should have 3.3V logic levels. The input impedance to this connector is approximately 50 Ω...
Evaluation Board Manual Preliminary PPC750FX Evaluation Board 10.12 Test Connections Access to selected points in the board circuits, not available through connectors or jumpers, is provided by small test connections. All of the test connections are small pads with a center hole. An electrical connection can be made to any of these test connections for test purposes.
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Evaluation Board Manual PPC750FX Evaluation Board Preliminary Table 10-13. Test Connections (Continued) Location Component Signal TP23 U3 System Controller MPP3 TP24 U3 System Controller MPP2 TP25 U3 System Controller MPP1 TP27 U3 System Controller MPP6 TP28 U3 System Controller MPP4...
Evaluation Board Manual Preliminary PPC750FX Evaluation Board 11. CPLD Programming This chapter contains logic of the CPLD (formerly FPGA) module and timing values for the signals associated with the CPLD. Table 11-1. Section Contents Description Page Programming—Registers and Control Functions Timing—Registers and Control Functions...
Evaluation Board Manual PPC750FX Evaluation Board Preliminary Table 11-2. CPLD I/O Pin List (Continued) Name Function GND+ pld25mhz Input VCCINT Power dev_adr[0] Bidir dev_adr[1] Bidir dev_adr[2] Bidir dev_adr[3] Bidir dev_adr[4] Bidir ldev_addr[20] Input cpufan_ok_n Input ldev_addr[19] Input 11.1.2 CPLD Logic The folllowing sections provided a representation of the logic of the complete CPLD in either graphical or code listing format.
Evaluation Board Manual Preliminary PPC750FX Evaluation Board 11.1.2.3 framcs Logic The following logic diagram defines the function of the logic in the framcs part of the CPLD: Date: May 6, 2003 framcs.bdf Project: top lpm_dff0 badr0 INPUT qadr0 data clock...
Evaluation Board Manual PPC750FX Evaluation Board Preliminary 11.1.2.4 decode_block Program The following code listing defines the function of the logic in the decode_block part of the CPLD: INCLUDE "lpm_ff.inc"; -- 10:30 AM Mar 26, 2003 INCLUDE "lpm_counter.inc"; SUBDESIGN decode_block sysreset_n : INPUT;...
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Evaluation Board Manual Preliminary PPC750FX Evaluation Board FLASH/SRAM/BIG : NODE; -- boot from SRAM BIG/SRAM/FLASH : NODE; -- boot BIG, then SRAM, flash on CS0 BIG/FLASH/SRAM : NODE; -- boot BIG, then flash, SRAM on CS0 halfclk : NODE; sram_cs_n : NODE;...
Evaluation Board Manual PPC750FX Evaluation Board Preliminary 11.1.2.5 registers2 Program The following code listing defines the function of the logic in the registers2 part of the CPLD: INCLUDE "lpm_ff.inc"; INCLUDE "lpm_mux.inc"; SUBDESIGN registers2 sysreset_n : INPUT; cstiming_n : INPUT; we_n0 : INPUT;...
Evaluation Board Manual Preliminary PPC750FX Evaluation Board 11.1.2.6 reset_block Program The following code listing defines the function of the logic in the reset_block part of the CPLD: INCLUDE "lpm_ff.inc"; SUBDESIGN reset_block 25Mclk : INPUT; rw_hreset : INPUT; rw_sreset : INPUT;...
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Evaluation Board Manual Preliminary PPC750FX Evaluation Board -- Cascade tff’s - create a 2 bit counter -- that runs at the full rate. AND the output bits together -- and whenever count = "11" a pulse is generated. -- Use that 1/4 rate pulse as an enable for the dff’s.
Evaluation Board Manual Preliminary PPC750FX Evaluation Board 11.1.2.7 misc Logic The following logic diagram defines the function of the logic in the misc part of the CPLD: LPM_COUNTER LPM_COMPARE cnt_en dataa[] pld25mhz pld25mhz INPUT datab[] aneb mpp_reset_out_n LCELL mpp_reset_out_n INPUT...
Evaluation Board Manual PPC750FX Evaluation Board Preliminary 11.2 Timing—Registers and Control Functions The timing data in the following tables are based on simulation. 11.2.1 Maximum Clock Frequency Table 11-4 provides the actual frequency at which the indicated clock is running, and the highest frequency at which it can be allowed to run before the period becomes shorter than the worst case signal propagation time.
Evaluation Board Manual PPC750FX Evaluation Board Preliminary 11.2.3 Pin-to-Pin Signal Delay Table 11-6 provides the input pin-to-output pin delay time for all signals that are not clocked through a register. Table 11-6. Pin-to-Pin Signal Delay Source Destination Longest Delay (ns)
Evaluation Board Manual PPC750FX Evaluation Board Preliminary 11.2.4 Setup and Hold Time Table 11-7 provides the minimum setup and hold time for the indicated input relative to the indicated clock. Table 11-7. Setup and Hold Time Input Clock Setup Time (ns)
Table 12-5, the component is not assembled if the DNP column contains TRUE. In some cases installation of DNP parts requires the removal of installed parts and constitutes a change in the design of the board. IBM does not support boards that have been modified by removing normally installed parts.
Evaluation Board Manual PPC750FX Evaluation Board Preliminary Figure 12-1. Example of a Component Placement List in the Schematics 7830 4260 7995 1355 1135 11130 6330 11120 The information provided in each column of the component placement table is described in Table 12-2: Table 12-2.
Evaluation Board Manual Preliminary PPC750FX Evaluation Board The normal procedure to locate a component is to look up the coordinates in the Component Placement table in the schematic diagram, then use the X and Y scales on the edge of the board to get to the approximate location of the component on the board.
Evaluation Board Manual PPC750FX Evaluation Board Preliminary 12.2 Debugging Tools Table 12-3 identifies components that are recommended as aids for hardware monitoring. None of these components are shipped in the board package. Table 12-3. Debugging Tools Quantity Description 184 Pin DIMM Analysis Probe Vendor 1: FuturePlus Inc.
Evaluation Board Manual Preliminary PPC750FX Evaluation Board 12.4 Board Bill of Materials Table 12-5 provides a complete list of all components used to manufacture the board assembly. In addition, all components that appear in the schematics but that are not actually assembled on the board (DNP column contains TRUE) appear in this table.
Evaluation Board Manual Preliminary PPC750FX Evaluation Board Index registers and control timing auxiliary materials clock-to-output pin-topin signal delay registers and control setup and hold time CPLD register definitions batteries bill of materials processor support auxiliary material in kit current monitoring...
Evaluation Board Manual Preliminary PPC750FX Evaluation Board Revision Log Revision Date Contents of Modification 06/10/03 Initial creation of the book. 750FXebm_revlog.fm Revision Log June 10, 2003 Page 115 of 115...