Pin-To-Pin Signal Delay; Table 11-6. Pin-To-Pin Signal Delay - IBM PPC750FX User Manual

Evaluation Board Manual
PPC750FX Evaluation Board

11.2.3 Pin-to-Pin Signal Delay

Table 11-6 provides the input pin-to-output pin delay time for all signals that are not clocked through a
register.

Table 11-6. Pin-to-Pin Signal Delay

Source
atx_ok_n
atx_ok_n
atx_ok_n
atx_ok_n
atx_ok_n
atx_ok_n
badr[0]
badr[0]
badr[0]
badr[0]
badr[0]
badr[0]
badr[0]
badr[0]
badr[0]
badr[0]
badr[0]
badr[1]
badr[1]
badr[1]
badr[1]
badr[1]
badr[1]
badr[1]
badr[1]
badr[1]
badr[1]
badr[1]
badr[2]
badr[2]
badr[2]
badr[2]
badr[2]
CPLD Programming
Page 96 of 115
Destination
cpu_trst_n
cpu0_hreset_n
cpu1_hreset_n
led_red_n
sysreset
sysreset_n
dev_adr[0]
dev_adr[1]
dev_adr[2]
dev_adr[3]
dev_adr[4]
dev_adr[5]
dev_adr[6]
dev_adr[7]
nvram_cs_n
uart_cs_n
write_n
dev_adr[0]
dev_adr[1]
dev_adr[2]
dev_adr[3]
dev_adr[4]
dev_adr[5]
dev_adr[6]
dev_adr[7]
nvram_cs_n
uart_cs_n
write_n
dev_adr[0]
dev_adr[1]
dev_adr[2]
dev_adr[3]
dev_adr[4]
Longest Delay (ns) Shortest Delay (ns)
14.200
10.900
14.200
5.300
10.300
10.300
8.700
8.700
8.700
8.700
8.700
8.700
8.700
8.700
14.300
5.600
6.400
8.700
8.700
8.700
8.700
8.700
8.700
8.700
8.700
14.300
5.600
6.400
8.700
8.700
8.700
8.700
8.700
Preliminary
14.200
10.500
14.200
5.300
10.300
10.300
5.600
5.600
5.600
5.600
5.600
5.600
5.600
5.600
14.300
5.600
5.600
5.600
5.600
5.600
5.600
5.600
5.600
5.600
5.600
14.300
5.600
5.600
5.600
5.600
5.600
5.600
5.600
750FXebm_ch11.fm
June 10, 2003