Table 2-2. Switch Settings; Table 2-3. Flash Configurations - IBM PPC750FX User Manual

Preliminary
The 8-bit wide Flash is installed at the top of the address space. Immediately below that Flash in the address
space is the SRAM. Switch #7 on switch U24 allows the exchange of the two blocks in the address space.
The intent of this SRAM is to aid in the debug of ROM boot code, not for speed enhancement. Flash contents
will be copied to SRAM, then SRAM will be placed at the top of the address space. ROM code can then be
debugged from SRAM, allowing the placement of unlimited software break points.
Note 1: A jumper at J8 can be installed to prevent any 32-bit Flash write operations.
Note 2: Caching the 8- or 32-bit Flash memories is not supported.
Table 2-2 and Table 2-3 describe the switch settings and the resulting configurations.

Table 2-2. Switch Settings

Configuration
1
2
3
4

Table 2-3. Flash Configurations

Configuration Address Range
0xFFF00000 to 0xFFFFFFFF
1 0xFFE00000 to 0xFFEFFFFF
0xFC000000 to 0xFDFFFFFF
0xFFF00000 to 0xFFFFFFFF
2 0xFFE00000 to 0xFFEFFFFF
0xFC000000 to 0xFDFFFFFF
0xFE000000 to 0xFFFFFFFF
0xFC100000 to 0xFC1FFFFF
3
0xFC000000 to 0xFC0FFFFF
0xFE000000 to 0xFFFFFFFF
0xFC100000 to 0xFC1FFFFF
4
0xFC000000 to 0xFC0FFFFF
Notes: 1. The reset vector of the PPC750FX is 0xFFF00100.
2. The base addresses of peripherals attached to the MV64360 system controller device are software dependent. The values
in the table above are used by the PPC750FX Evaluation Kit Software. Other software environments may use different
values for the peripheral base addresses.
750FXebm_ch2.fm
June 10, 2003
U17 SW6 U24 SW 7
ON
ON
OFF
OFF
8-bit Flash controlled by BootCS
8-bit SRAM controlled by BootCS
32-bit Flash controlled by DevCS0
8-bit SRAM controlled by BootCS
8-bit Flash controlled by BootCS
32-bit Flash controlled by DevCS0
32-bit Flash controlled by BootCS
8-bit Flash controlled by DevCS0
8-bit SRAM controlled by DevCS0.
Note: In configuration 3, SRAM is at the beginning of the DevCS0 memory
range followed by 8-bit wide Flash.
32-bit Flash controlled by BootCS
8-bit SRAM controlled by DevCS0
8-bit Flash controlled by DevCS0.
Note: In configuration 4, 8-bit wide Flash is at the beginning of the DevCS0
memory range followed by SRAM.
ON 8-bit boot, Flash at higher address
OFF 8-bit boot, SRAM at higher address
ON 32-bit boot, Flash at higher address
OFF 32-bit boot, SRAM at higher address
Module(s) selected
Evaluation Board Manual
PPC750FX Evaluation Board
Description
Board Design
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