IBM PPC750FX User Manual page 74

Evaluation Board Manual
PPC750FX Evaluation Board
Table 11-2. CPLD I/O Pin List (Continued)
Name
~TMS~
write_n
uart_cs_n
VCCIO1
nvram_cs_n
led1
led_red_n
ignore_fans_n
mpp0_sreset_n
cpu1_chkstop_n
sysreset
GND
dev_adr[5]
dev_adr[6]
dev_adr[7]
sysreset_n
mpp1_hreset_n
NOFAN_N
sram_cs_n
VCCIO1
small_flash_cs_n
read_n
big_flash_cs_n
GND
VCCINT
badr[0]
initact
flash_n/sram_sel
GND
lcs_n[2]
pwrgd
switch_a
testpin_c
testpin_b
testpin_a
textpin_d
VCCIO2
CPLD Programming
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Pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Preliminary
Function
Input
Output
Output
Power
Output
Output
Output
Input
Input
Input
Output
Gnd
Bidir
Bidir
Bidir
Output
Input
Output
Output
Power
Output
Output
Output
Gnd
Power
Input
Input
Input
Gnd
Input
Input
Input
Output
Output
Output
Output
Power
750FXebm_ch11.fm
June 10, 2003