Registers2 Program - IBM PPC750FX User Manual

Evaluation Board Manual
PPC750FX Evaluation Board

11.1.2.5 registers2 Program

The following code listing defines the function of the logic in the registers2 part of the CPLD:
INCLUDE "lpm_ff.inc";
INCLUDE "lpm_mux.inc";
SUBDESIGN registers2
(
sysreset_n
cstiming_n
we_n0
ale
dev_ad[7..0]
-- " "
fpga_cs_n
badr[2..0]
target/host_n
flash_n/sram_sel : INPUT; -- Flash/SRAM switch
bootsmall_n
switch_a
switch_b
ATX_OK_N
ldevR_W_n
lboot_cs_n
led0
led1
led2
cpu0_smi_n
cpu1_smi_n
cpu_tben
cpu_mcp0
cpu_mcp1
read_oe
mpp_block_n
)
VARIABLE
ldev_adr[8..3]
PLDversion_sel : node;-- register 0
PLDversion[7..0] : NODE;
Register1_sel : NODE;-- register 1
CPLD Programming
Page 84 of 115
: INPUT;
: INPUT;
: INPUT; -- Dev_we_n[0] from controller
: INPUT; -- for internal latching of address/control
: BIDIR; -- when input address/control from system controller it needs latched,
-- when output to system controller it is data
: INPUT; -- uses lcs_n1
: INPUT; -- burst addresses
: INPUT; -- PCI switch
: INPUT; -- Boot switch
: INPUT; -- spare switch A
: INPUT; -- spare switch B
: INPUT; -- low if ATX power is on.
: OUTPUT; -- latched directly from muxed address/data bus
: OUTPUT; -- latched directly from muxed address/data bus
: OUTPUT;
: OUTPUT;
: OUTPUT;
: OUTPUT; -- 2.5V logic to CPU0, resets to high
: OUTPUT; -- 2.5V logic to CPU1, resets to high
: OUTPUT; -- 2.5V logic to both CPUs, resets to high
: OUTPUT; -- 2.5V logic to both CPUs, resets to high
: OUTPUT; -- 2.5V logic to both CPUs, resets to high
: OUTPUT;
: OUTPUT; -- 1 = pass mpp_Xreset pins
: NODE; -- shifting addresses from [7..2] to match other designs.
Preliminary
750FXebm_ch11.fm
June 10, 2003