Device Bank 2 Parameters (Uarts); Table 4-4. Device Bank 2 Parameters = 0X8C002Bd6 - IBM PPC750FX User Manual

Evaluation Board Manual
PPC750FX Evaluation Board

4.2.3 Device Bank 2 Parameters (UARTs)

Table 4-4. Device Bank 2 Parameters = 0x8C002BD6

Field
TurnOff
Acc2First
Acc2Next
ALE2Wr
WrLow
WrHigh
DevWidth
TurnOffExt
Acc2FirstExt
Acc2NextExt
ALE2WrExt
WrLowExt
WrHighExt
BadrSkew
DPEn
Reserved
Programming the System Controller
Page 34 of 115
Value (bin)
Number of Sysclk cycles that the system controller does not drive the
110
address/data bus after completion of a device read
Number of Sysclk cycles from the de-assertion of ALE to the cycle that the
1010
first read data is sampled
Number of Sysclk cycles in a burst read access between the cycle that
0111
samples data N to the cycle that samples data N+1
101 Number of Sysclk cycles from ALE de-assertion to the assertion of Wr[0]
000 Number of Sysclk cycles that Wr[0] is active
Number of Sysclk cycles between data beats of a burst write that Wr[0] is
000
held in-active. BAdr and data are held valid for WrHigh-1 cycles
00 Device width of 8 bits
0 TurnOff extension (most significant bit)
0 Acc2First extension (most significant bit)
0 Acc2Next extension (most significant bit)
0 ALE2Wr extension (most significant bit)
1 WrLow extension (most significant bit)
1 WrHigh extension (most significant bit)
00 Number of Sysclk cycles from when BAdr changes to the read of the data
0 Parity Disabled
1
Comment
750FXebm_ch4.fm
June 10, 2003
Preliminary